MC68HC908LK24 MOTOROLA [Motorola, Inc], MC68HC908LK24 Datasheet - Page 142

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MC68HC908LK24

Manufacturer Part Number
MC68HC908LK24
Description
Microcontrollers
Manufacturer
MOTOROLA [Motorola, Inc]
Datasheet

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System Integration Module (SIM)
9.3 SIM Bus Clock Control and Generation
Data Sheet
142
Note: Writing a logic 0 clears SBSW.
Addr.
$FE00
$FE01
$FE03
$FE04
$FE05
$FE06
SIM Break Status Register
SIM Reset Status Register
Interrupt Status Register 1
Interrupt Status Register 2
Interrupt Status Register 3
SIM Break Flag Control
Register Name
(SBFCR)
Register
(SRSR)
(SBSR)
(INT1)
(INT2)
(INT3)
The bus clock generator provides system clock signals for the CPU and
peripherals on the MCU. The system clocks are generated from an
incoming clock, CGMOUT, as shown in
from either the oscillator module or from the on-chip PLL. (See
8. Clock Generator Module
Reset:
Reset:
Reset:
Reset:
Reset:
Read:
Write:
Read:
Write:
Read:
Write:
Read:
Write:
Read:
Write:
Read:
Write:
POR:
Freescale Semiconductor, Inc.
Figure 9-2. SIM I/O Register Summary
For More Information On This Product,
BCFE
Bit 7
POR
IF14
IF6
R
R
R
R
1
0
0
0
0
0
System Integration Module (SIM)
Go to: www.freescale.com
= Unimplemented
IF13
PIN
IF5
R
R
R
R
R
6
0
0
0
0
0
COP
IF12
IF4
R
R
R
R
R
5
0
0
0
0
0
(CGM).)
ILOP
IF11
IF3
R
R
R
R
R
4
0
0
0
0
0
Figure
ILAD
IF10
IF18
IF2
R
R
R
R
R
R
3
0
0
0
0
MC68HC908LJ24/LK24 — Rev. 2
9-3. This clock can come
= Reserved
IF17
IF1
IF9
R
R
R
R
R
2
0
0
0
0
0
SBSW
Note
IF16
LVI
IF8
R
R
R
R
1
0
0
0
0
0
0
MOTOROLA
Section
Bit 0
IF15
IF7
R
R
R
R
R
0
0
0
0
0
0

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