MC68HC908LK24 MOTOROLA [Motorola, Inc], MC68HC908LK24 Datasheet - Page 235

• Manufacturer Part Number: MC68HC908LK24
• Description: Microcontrollers
• Manufacturer: MOTOROLA [Motorola, Inc]

12.10.4 RTC Control Register 2 (RTCCR2)
MC68HC908LJ24/LK24 — Rev. 2
MOTOROLA
†† Reset by POR only.
* COMEN and RTCE bits are write-protected; unprotect by a write sequence to RTCWE[1:0] in RTCCOMR.
Address:
SECIE — Second Interrupt Enable
TB1IE — Timebase 1 Interrupt Enable
TB2IE — Timebase 2 Interrupt Enable
The RTC control register 2 (RTCCR2) contains control and clock
selection bits for RTC operation.
COMEN — RTC Compensation Enable
Reset:
Read:
Write:
This read/write bit enables the second flag, SECF, to generate CPU
interrupt requests. Reset clears the SECIE bit.
This read/write bit enables the timebase1 flag, TB1F, to generate
CPU interrupt requests. Reset clears the TB1IE bit.
This read/write bit enables the timebase2 flag, TB2F, to generate
CPU interrupt requests. Reset clears the TB2IE bit.
This read/write bit enables the clock compensation mechanism for
CGMXCLK frequency errors. Reset has no effect on COMEN bit.
Freescale Semiconductor, Inc.
For More Information On This Product,
1 = SECF enabled to generate CPU interrupt
0 = SECF not enabled to generate CPU interrupt
1 = TB1F enabled to generate CPU interrupt
0 = TB1F not enabled to generate CPU interrupt
1 = TB2F enabled to generate CPU interrupt
0 = TB2F not enabled to generate CPU interrupt
1 = Compensation mechanism enabled
0 = Compensation mechanism not enabled
COMEN*
$0043
U
Figure 12-9. RTC Control Register 2 (RTCCR2)
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Real Time Clock (RTC)
CHRCLR
= Unimplemented
0
0
CHRE
0
RTCE*
0
††
TBH
0
0
0
Real Time Clock (RTC)
0
0
RTC Registers
Data Sheet
0
0
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