MC68HC908LK24 MOTOROLA [Motorola, Inc], MC68HC908LK24 Datasheet - Page 344

• Manufacturer Part Number: MC68HC908LK24
• Description: Microcontrollers
• Manufacturer: MOTOROLA [Motorola, Inc]

Analog-to-Digital Converter (ADC)
16.8.2 ADC Data Register
Data Sheet
344
Addr.
$003D
Addr.
$003D
$003E
$003E
ADC Data Register High
ADC Data Register High
ADC Data Register Low
ADC Data Register Low
Register Name
Register Name
Figure 16-5. ADRH and ADRL in 8-Bit Truncated Mode
(ADRH)
(ADRH)
Figure 16-6. ADRH and ADRL in Right Justified Mode
(ADRL)
(ADRL)
The ADC data register consist of a pair of 8-bit registers: high byte
(ADRH), and low byte (ADRL). This pair form a 16-bit register to store
the 10-bit ADC result for the selected ADC result justification mode.
In 8-bit truncated mode, the ADRL holds the eight most significant bits
(MSBs) of the 10-bit result. The ADRL is updated each time an ADC
conversion completes. In 8-bit truncated mode, ADRL contains no
interlocking with ADRH. (See
Truncated
In right justified mode the ADRH holds the two MSBs, and the ADRL
holds the eight least significant bits (LSBs), of the 10-bit result. ADRH
and ADRL are updated each time a single channel ADC conversion
completes. Reading ADRH latches the contents of ADRL. Until ADRL is
read all subsequent ADC results will be lost.
(See
Reset:
Reset:
Reset:
Reset:
Read:
Write:
Read:
Write:
Read:
Write:
Read:
Write:
Freescale Semiconductor, Inc.
For More Information On This Product,
Figure 16-6 . ADRH and ADRL in Right Justified
Bit 7
Bit 7
AD9
AD7
Analog-to-Digital Converter (ADC)
R
R
R
R
0
0
0
0
0
0
Mode.)
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AD8
AD6
R
R
R
R
6
0
0
0
6
0
0
0
AD7
AD5
R
R
R
R
5
0
0
0
5
0
0
0
Figure 16-5 . ADRH and ADRL in 8-Bit
AD6
AD4
R
R
R
R
4
0
0
0
4
0
0
0
AD5
AD3
R
R
R
R
3
0
0
0
3
0
0
0
MC68HC908LJ24/LK24 — Rev. 2
AD4
AD2
R
R
R
R
2
0
0
0
2
0
0
0
Mode.)
AD3
AD9
AD1
R
R
R
R
1
0
0
0
1
0
0
MOTOROLA
Bit 0
Bit 0
AD2
AD8
AD0
R
R
R
R
0
0
0
0
0