MC68HC908LK24 MOTOROLA [Motorola, Inc], MC68HC908LK24 Datasheet - Page 324

• Manufacturer Part Number: MC68HC908LK24
• Description: Microcontrollers
• Manufacturer: MOTOROLA [Motorola, Inc]

Multi-Master IIC Interface (MMIIC)
15.5.3 Multi-Master IIC Master Control Register (MIMCR)
Data Sheet
324
Address:
REPSEN — Repeated Start Enable
MMALIF — Multi-Master Arbitration Lost Interrupt Flag
MMNAKIF — No Acknowledge Interrupt Flag
Reset:
Figure 15-4. Multi-Master IIC Master Control Register (MIMCR)
Read: MMALIF MMNAKIF
Write:
Freescale Semiconductor, Inc.
This bit is set to enable repeated START signal to be generated when
in master mode transfer (MMAST = 1). The REPSEN bit is cleared by
hardware after the completion of repeated START signal or when the
MMAST bit is cleared. Reset clears this bit.
This flag is set when software attempt to set MMAST but the MMBB
has been set by detecting the start condition on the lines or when the
MMIIC is transmitting a "1" to SDA line but detected a "0" from SDA
line in master mode – an arbitration loss. This bit generates an
interrupt request to the CPU if the MMIEN bit in MMCR is also set.
This bit is cleared by writing "0" to it or by reset.
This flag is only set in master mode (MMAST = 1) when there is no
acknowledge bit detected after one data byte or calling address is
transferred. This flag also clears MMAST. MMNAKIF generates an
interrupt request to CPU if the MMIEN bit in MMCR is also set. This
bit is cleared by writing "0" to it or by reset.
For More Information On This Product,
1 = Repeated START signal will be generated if MMAST bit is set
0 = No repeated START signal will be generated
1 = Lost arbitration in master mode
0 = No arbitration lost
1 = No acknowledge bit detected
0 = Acknowledge bit detected
$006A
Bit 7
Multi-Master IIC Interface (MMIIC)
0
0
Go to: www.freescale.com
= Unimplemented
6
0
0
MMBB
5
0
MMAST
4
0
MMRW
3
0
MC68HC908LJ24/LK24 — Rev. 2
MMBR2
2
0
MMBR1
1
0
MOTOROLA
MMBR0
Bit 0
0