MC68HC908LK24 MOTOROLA [Motorola, Inc], MC68HC908LK24 Datasheet - Page 147

• Manufacturer Part Number: MC68HC908LK24
• Description: Microcontrollers
• Manufacturer: MOTOROLA [Motorola, Inc]

9.4.2.2 Computer Operating Properly (COP) Reset
MC68HC908LJ24/LK24 — Rev. 2
MOTOROLA
CGMOUT
PORRST
OSC1
IRST
ICLK
RST
IAB
An input to the SIM is reserved for the COP reset signal. The overflow of
the COP counter causes an internal reset and sets the COP bit in the
SIM reset status register (SRSR). The SIM actively pulls down the RST
pin for all internal reset sources.
To prevent a COP module timeout, write any value to location $FFFF.
Writing to location $FFFF clears the COP counter and bits 12 through 5
of the SIM counter. The SIM counter output, which occurs at least every
2
serviced as soon as possible out of reset to guarantee the maximum
amount of time before the first timeout.
The COP module is disabled if the RST pin or the IRQ pin is held at V
while the MCU is in monitor mode. The COP module can be disabled
only through combinational logic conditioned with the high voltage signal
on the RST or the IRQ pin. This prevents the COP from becoming
disabled as a result of external noise. During a break state, V
RST pin disables the COP module.
13
CYCLES
Freescale Semiconductor, Inc.
4096
– 2
For More Information On This Product,
4
ICLK cycles, drives the COP counter. The COP should be
Figure 9-7. POR Recovery
System Integration Module (SIM)
CYCLES
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32
CYCLES
32
System Integration Module (SIM)
$FFFE
Reset and System Initialization
$FFFF
TST
Data Sheet
on the
TST
147