MC68HC908LK24 MOTOROLA [Motorola, Inc], MC68HC908LK24 Datasheet - Page 144
MC68HC908LK24
Manufacturer Part Number
MC68HC908LK24
Description
Microcontrollers
Manufacturer
MOTOROLA [Motorola, Inc]
Datasheet
1.MC68HC908LK24.pdf
(465 pages)
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System Integration Module (SIM)
9.3.3 Clocks in Stop Mode and Wait Mode
9.4 Reset and System Initialization
Data Sheet
144
Upon exit from stop mode by an interrupt, break, or reset, the SIM allows
ICLK to clock the SIM counter. The CPU and peripheral clocks do not
become active until after the stop delay timeout. This timeout is
selectable as 4096 or 32 ICLK cycles. (See
In wait mode, the CPU clocks are inactive. The SIM also produces two
sets of clocks for other modules. Refer to the wait mode subsection of
each module to see if the module is active or inactive in wait mode.
Some modules can be programmed to be active in wait mode.
The MCU has these reset sources:
All of these resets produce the vector $FFFE:$FFFF ($FEFE:$FEFF in
monitor mode) and assert the internal reset signal (IRST). IRST causes
all registers to be returned to their default values and all modules to be
returned to their reset states.
An internal reset clears the SIM counter (see
external reset does not. Each of the resets sets a corresponding bit in
the SIM reset status register (SRSR). (See
Freescale Semiconductor, Inc.
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For More Information On This Product,
Power-on reset module (POR)
External reset pin (RST)
Computer operating properly module (COP)
Low-voltage inhibit module (LVI)
Illegal opcode
Illegal address
System Integration Module (SIM)
Go to: www.freescale.com
MC68HC908LJ24/LK24 — Rev. 2
9.8 SIM
9.7.2 Stop
9.5 SIM
Registers.)
Counter), but an
Mode.)
MOTOROLA
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