MC68HC908LK24 MOTOROLA [Motorola, Inc], MC68HC908LK24 Datasheet - Page 426
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MC68HC908LK24
Manufacturer Part Number
MC68HC908LK24
Description
Microcontrollers
Manufacturer
MOTOROLA [Motorola, Inc]
Datasheet
1.MC68HC908LK24.pdf
(465 pages)
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Low-Voltage Inhibit (LVI)
22.6 Low-Power Modes
22.6.1 Wait Mode
22.6.2 Stop Mode
Data Sheet
426
NOTE:
LVIIE — LVI Interrupt Enable Bit
LVIIF — LVI Interrupt Flag
LVIIACK — LVI Interrupt Acknowledge Bit
The STOP and WAIT instructions put the MCU in low power-
consumption standby modes.
If enabled, the LVI module remains active in wait mode. If enabled to
generate resets or interrupts, the LVI module can generate a reset or an
interrupt and bring the MCU out of wait mode.
If enabled in stop mode (LVISTOP = 1), the LVI module remains active
in stop mode. If enabled to generate resets or interrupts, the LVI module
can generate a reset or an interrupt and bring the MCU out of stop mode.
If enabled to generate both resets and interrupts, there will be no LVI
interrupts, as resets have a higher priority.
Freescale Semiconductor, Inc.
This read/write bit enables the LVIIF bit to generate CPU interrupt
requests. Reset clears the LVIIE bit.
This clearable, read-only flag is set whenever the LVIOUT bit toggles.
Reset clears the LVIIF bit.
Writing a logic 1 to this write-only bit clears the LVI interrupt flag,
LVIIF. LVIIACK always reads as logic 0.
For More Information On This Product,
1 = LVIIF can generate CPU interrupt requests
0 = LVIIF cannot generate CPU interrupt requests
1 = LVIOUT has toggled
0 = LVIOUT has not toggled
1 = Clears LVIIF bit
0 = No effect
Go to: www.freescale.com
Low-Voltage Inhibit (LVI)
MC68HC908LJ24/LK24 — Rev. 2
MOTOROLA
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