MPC8313EZQADDC Freescale Semiconductor, MPC8313EZQADDC Datasheet - Page 1085

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MPC8313EZQADDC

Manufacturer Part Number
MPC8313EZQADDC
Description
Microprocessors - MPU 8313 REV2.2 PB W/ENC
Manufacturer
Freescale Semiconductor
Datasheet

Specifications of MPC8313EZQADDC

Processor Series
MPC8313E
Core
e300
Data Bus Width
16 bit
Maximum Clock Frequency
133 MHz
Program Memory Size
16 KB
Data Ram Size
16 KB
Interface Type
I2C
Mounting Style
SMD/SMT
Package / Case
PBGA
Number Of Programmable I/os
32
Number Of Timers
4
Chapter 17
I
This chapter describes the two inter-IC (IIC or I
for most intents, the I
necessary, differences between the two controllers are noted.
17.1
The inter-IC (IIC or I
bus that provides a simple, efficient method of data exchange between this device and other devices, such
as microcontrollers, EEPROMs, real-time clock devices, A/D converters, and LCDs.
block diagram of the I
The two-wire I
bus allows the connection of additional devices to the bus for expansion and system development. The bus
Freescale Semiconductor
2
C Interfaces
Introduction
MPC8313E PowerQUICC™ II Pro Integrated Processor Family Reference Manual, Rev. 2
2
I2CDSRR
C bus minimizes interconnections between devices. The synchronous, multiple-master I
2
2
C) bus is a two-wire—serial data (SDA) and serial clock (SCL)—bidirectional serial
2
C interfaces are identical and are described as a single generic controller. Where
Address and Control
C interface.
Addr Decode
Digital Filter
SDA
Input Sync
I2CADR
Control
Clock
and
and
SCL
Figure 17-1. I
I2CFDR
2
C) bus interfaces implemented on this device. Note that
2
Repeated
Arbitration
C Block Diagram
START/
START
Control
STOP/
I2CCR
and
arb_lost
I2CSR
Interrupt
Shift Register
In/Out Data
Compare
Address
Data Mux
I2CDR
Data
Figure 17-1
shows a
17-1
2
C

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