MPC8313EZQADDC Freescale Semiconductor, MPC8313EZQADDC Datasheet - Page 83
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MPC8313EZQADDC
Manufacturer Part Number
MPC8313EZQADDC
Description
Microprocessors - MPU 8313 REV2.2 PB W/ENC
Manufacturer
Freescale Semiconductor
Datasheet
1.MPC8313CZQADDC.pdf
(1214 pages)
Specifications of MPC8313EZQADDC
Processor Series
MPC8313E
Core
e300
Data Bus Width
16 bit
Maximum Clock Frequency
133 MHz
Program Memory Size
16 KB
Data Ram Size
16 KB
Interface Type
I2C
Mounting Style
SMD/SMT
Package / Case
PBGA
Number Of Programmable I/os
32
Number Of Timers
4
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— Support for two x16 devices
— The following SDRAM configurations are supported:
— Support for up to 8 simultaneous open pages
— Sleep-mode support for SDRAM self refresh
— Supports auto refresh
— On-the-fly power management using CKE
— Registered DIMM support
— 2.5-V SSTL2 compatible I/O for DDR1, 1.8-V SSTL_18 compatible I/O for DDR2
Two enhanced three-speed Ethernet controllers (eTSECs)
— Backward compatible with MPC8548 (PowerQUICC III) eTSEC
— Three-speed support (10/100/1000 Mbps)
— On-chip high-speed serial interface to external SGMII PHY interface
— Two SGMII interfaces, two RGMII/RTBI/MII/RMII interfaces.
— Two controllers designed to comply with IEEE Std 802.3®, 802.3u®, 802.3x®, 802.3z®,
— Support for IEEE Std 1588™
— Support for two full-duplex FIFO interface modes
— Multiple PHY interface configurations
— Support for Wake-on-Magic Packet™, a method to bring the device from standby to full
— TCP/IP acceleration and QoS features available
— Full- and half-duplex Ethernet support (1000 Mbps supports only full-duplex):
– Up to two physical banks (chip selects), each bank up to 1 Gbyte independently addressable
– 64-Mbit to 1-Gbit devices with x8/x16/x32 data ports (no direct x4 support). Some 2-Gbit
– One 16-bit device or two 8-bit devices on a 16-bit bus, or one 32-bit device or two 16-bit
802.3ac®, and 802.3ab®
operating mode
– IP v4 and IP v6 header recognition on receive
– IP v4 header checksum verification and generation
– TCP and UDP checksum verification and generation
– Per-packet configurable acceleration
– Recognition of VLAN, stacked (queue in queue) VLAN, 802.2, PPPoE session, MPLS
– Supported in all FIFO modes
– Transmission from up to eight physical queues
– Reception to up to eight physical queues
– IEEE Std. 802.3 full-duplex flow control (automatic PAUSE frame generation or
MPC8313E PowerQUICC™ II Pro Integrated Processor Family Reference Manual, Rev. 2
devices are supported depending on the internal device configuration.
devices or four 8-bit devices on a 32-bit bus
stacks, and ESP/AH IP-security headers
software-programmed PAUSE frame generation and recognition)
Overview
1-3
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