MPC8313EZQADDC Freescale Semiconductor, MPC8313EZQADDC Datasheet - Page 404

• Manufacturer Part Number: MPC8313EZQADDC
• Description: Microprocessors - MPU 8313 REV2.2 PB W/ENC
• Manufacturer: Freescale Semiconductor

Specifications of MPC8313EZQADDC

• Processor Series: MPC8313E
• Core: e300
• Data Bus Width: 16 bit
• Maximum Clock Frequency: 133 MHz
• Program Memory Size: 16 KB
• Data Ram Size: 16 KB
• Interface Type: I2C
• Mounting Style: SMD/SMT
• Package / Case: PBGA
• Number Of Programmable I/os: 32
• Number Of Timers: 4

DDR Memory Controller
Table 9-6
9.4.1.2
The chip select configuration (CSn_CONFIG) registers shown in
and set the number of row and column bits used for each chip select. These registers should be loaded with
the correct number of row and column bits for each SDRAM. Because CSn_CONFIG[ROW_BITS_CS_n,
COL_BITS_CS_n] establish address multiplexing, the user should take great care to set these values
correctly.
If chip select interleaving is enabled, then all fields in the lower interleaved chip select are used, and the
other registers’ fields are unused, with the exception of the ODT_RD_CFG and ODT_WR_CFG fields.
For example, if chip selects 0 and 1 are interleaved, all fields in CS0_CONFIG are used, but only the
ODT_RD_CFG and ODT_WR_CFG fields in CS1_CONFIG are used.
Table 9-7
9-10
Offset 0x080, 0x084
Reset
Reset
16–23
24–31
8–15
Bits
Bits
0–7
1–7
0
W
W
R
R
CS_ n _ EN
BA_BITS_CS_ n
Name
SA n
EA n
describes the CSn_BNDS register fields.
describes the CSn_CONFIG register fields.
—
—
16
0
CS_ n _EN
Chip Select Configuration (CS n _CONFIG)
MPC8313E PowerQUICC™ II Pro Integrated Processor Family Reference Manual, Rev. 2
Name
Reserved
Starting address for chip select (bank) n. This value is compared against the 8 msbs of the 32-bit address.
Reserved
Ending address for chip select (bank) n. This value is compared against the 8 msbs of the 32-bit address.
—
17
1
Figure 9-3. Chip Select Configuration Register (CS n _CONFIG)
18
Chip select n enable
0 Chip select n is not active
1 Chip select n is active and assumes the state set in CS n _BNDS.
Reserved
—
Table 9-7. CS n _CONFIG Field Descriptions
Table 9-6. CS n_ BNDS Field Descriptions
—
20
ROW_BITS_CS_ n
21
All zeros
All zeros
23
7
Description
AP_ n _EN
24
8
Description
Figure 9-3
ODT_RD_CFG
9
—
enable the DDR chip selects
11
—
12
28
Freescale Semiconductor
Access: Read/Write
COL_BITS_CS_ n
ODT_WR_CFG
13
29
15
31