MPC8313EZQADDC Freescale Semiconductor, MPC8313EZQADDC Datasheet - Page 796

• Manufacturer Part Number: MPC8313EZQADDC
• Description: Microprocessors - MPU 8313 REV2.2 PB W/ENC
• Manufacturer: Freescale Semiconductor

Specifications of MPC8313EZQADDC

• Processor Series: MPC8313E
• Core: e300
• Data Bus Width: 16 bit
• Maximum Clock Frequency: 133 MHz
• Program Memory Size: 16 KB
• Data Ram Size: 16 KB
• Interface Type: I2C
• Mounting Style: SMD/SMT
• Package / Case: PBGA
• Number Of Programmable I/os: 32
• Number Of Timers: 4

Enhanced Three-Speed Ethernet Controllers
15.5.3.5.14 MAC Station Address Part 2 Register (MACSTNADDR2)
The MACSTNADDR2 register is written by the user.
MACSTNADDR2 register.
Table 15-53
15.5.3.5.15 MAC Exact Match Address 1–15 Part 1 Registers
The MAC01ADDR1–MAC15ADDR1 registers are written by the user with the unicast or multicast
addresses aliasing the MAC.
registers. The value of the address written into MACxADDR1 and MACnADDR2 is byte reversed from
how it would appear in the DA field of a frame in memory. For example, for a MAC address of
0x12345678ABCD, MACnADDR1 is set to 0xCDAB7856 and MACnADDR2 is set to 0x34120000. For
any valid, non-zero MAC address received, exact match registers can be excluded individually by clearing
them to all zero bytes.
15-78
Offset eTSEC1:0x2_4544; eTSEC2:0x2_5544
Reset
Offset eTSEC1:0x2_4548+8× n ; eTSEC2:0x2_5548+8× n
Reset
W
W
R
R
16–31
8–15
0–7
Bit
Station Address, 2nd Octet
0
0
Exact Match Address,
describes the fields of the MACSTNADDR2 register.
MPC8313E PowerQUICC™ II Pro Integrated Processor Family Reference Manual, Rev. 2
(MAC01ADDR1–MAC15ADDR1)
6th Octet
Station Address, 2nd Octet
Station Address, 1st Octet
Figure 15-50. MAC Exact Match Address n Part 1 Register Definition
Figure 15-49. MAC Station Address Part 2 Register Definition
Name
—
Table 15-53. MACSTNADDR2 Field Descriptions
Figure 15-50
7
7
8
8
Station Address, 1st Octet
Exact Match Address,
5th Octet
This field holds the second octet of the station address. The second
octet (station address bits 8
This field holds the first octet of the station address. The first octet
(station address bits 0
Reserved
describes the definition for all of the fifteen MACnADDR1
All zeros
All zeros
Figure 15-49
15 16
15 16
Exact Match Address,
–
7) defaults to a value of 0x0.
4th Octet
Description
–
15) defaults to a value of 0x0.
describes the definition for the
23 24
—
Exact Match Address,
Freescale Semiconductor
Access: Read/Write
Access: Read/Write
3rd Octet
31
31