MPC8313EZQADDC Freescale Semiconductor, MPC8313EZQADDC Datasheet - Page 362

• Manufacturer Part Number: MPC8313EZQADDC
• Description: Microprocessors - MPU 8313 REV2.2 PB W/ENC
• Manufacturer: Freescale Semiconductor

Specifications of MPC8313EZQADDC

• Processor Series: MPC8313E
• Core: e300
• Data Bus Width: 16 bit
• Maximum Clock Frequency: 133 MHz
• Program Memory Size: 16 KB
• Data Ram Size: 16 KB
• Interface Type: I2C
• Mounting Style: SMD/SMT
• Package / Case: PBGA
• Number Of Programmable I/os: 32
• Number Of Timers: 4

Integrated Programmable Interrupt Controller (IPIC)
The IPIC receives the following types of interrupts:
The interrupt controller provides the ability to mask each interrupt source. Any source that can be caused
by multiple events are also maskable.
When the IPIC receives an internal or external interrupt, its configuration register is checked to determine
if it should be routed off-chip (to the external PCI_INTA) or serviced as a normal external interrupt by the
processor core (through the int signal). As a third alternative, if the incoming interrupt has been configured
as a critical or system management interrupt, the IPIC completes the processing of the interrupt by
asserting cint or smi to the core. The assertion of the cint or smi signal to the core causes the interrupt to
be serviced as a critical or a system management interrupt, respectively.
8.2
The IPIC unit implements the following features:
8.3
The IPIC unit can operate in the core enable or core disable mode.
8.3.1
In core enable mode, all internal interrupts (including those from the PCI block) are routed to and from the
IPIC; the interrupts are sent to the PowerPC core. The DMA controller can optionally (depending on the
programming of the DMA registers) steer its interrupt to the PCI host through the PCI_INTA signal.
8-4
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External interrupt—triggered by the off-chip signals (IRQn) listed in
Internal interrupts—on-chip interrupts, triggered by the sources listed in
External and internal non-maskable machine check conditions, signaled by the sources listed in
Table 8-21
Functional and programming compatibility with the MPC8260 interrupt controller
Support for external and internal discrete vectorized interrupt sources
Support for external and internal non-maskable machine check conditions, signaled by mcp
Programmable highest priority request (can be programmed to support a critical (cint) or system
management interrupt (smi) type)
Two programmable priority mixed groups of four on-chip and four external interrupt signals with
two priority schemes for each group: grouped and spread
Two programmable priority internal groups of eight on-chip interrupt signals with two priority
schemes for each group: grouped and spread
Two highest priority interrupts from each group can be programmed to support a critical or system
management interrupt type
External and internal interrupts directed to host processor
Unique vector number for each interrupt source
Features
Modes of Operation
Core Enable Mode
MPC8313E PowerQUICC™ II Pro Integrated Processor Family Reference Manual, Rev. 2
through mcp
Table 8-1
Table 8-7
Freescale Semiconductor
and
Table 8-9