MPC8313EZQADDC Freescale Semiconductor, MPC8313EZQADDC Datasheet - Page 301

Manufacturer Part Number

MPC8313EZQADDC

Microprocessors - MPU 8313 REV2.2 PB W/ENC

Manufacturer

Freescale Semiconductor

Processor Series

Data Bus Width

Maximum Clock Frequency

Program Memory Size

Data Ram Size

Interface Type

Mounting Style

Package / Case

Number Of Programmable I/os

Number Of Timers

By following this flow, the e300 core remains in low power state while the rest of the system is operational,

and does not get out of this state as a result of any interrupt or time-based event.

Freescale Semiconductor

2. Clear PMCCR[SLPEN] and disable the core time base unit by clearing SPCR[TBEN]. See

3. The e300 core enters low power state by accessing the HID0 register.

4. Set ACR[COREDIS] in the system arbiter register with an external master (that is, PCI). This

Section 5.3.2.4, “System Priority and Configuration Register (SPCR),”

steers all device interrupts to the PCI_INTA so the core cannot receive any interrupt requests.

MPC8313E PowerQUICC™ II Pro Integrated Processor Family Reference Manual, Rev. 2

Make sure that the core cannot receive any interrupt requests during the time

interval between setting HID0 and setting ACR[COREDIS]. This can be

achieved if the rest of the system is idle (during the initialization).

for more information.

System Configuration