MPC8313EZQADDC Freescale Semiconductor, MPC8313EZQADDC Datasheet - Page 595
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MPC8313EZQADDC
Manufacturer Part Number
MPC8313EZQADDC
Description
Microprocessors - MPU 8313 REV2.2 PB W/ENC
Manufacturer
Freescale Semiconductor
Datasheet
1.MPC8313CZQADDC.pdf
(1214 pages)
Specifications of MPC8313EZQADDC
Processor Series
MPC8313E
Core
e300
Data Bus Width
16 bit
Maximum Clock Frequency
133 MHz
Program Memory Size
16 KB
Data Ram Size
16 KB
Interface Type
I2C
Mounting Style
SMD/SMT
Package / Case
PBGA
Number Of Programmable I/os
32
Number Of Timers
4
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access to the PCI controller’s internal PCI configuration registers. The PCI registers,
PCI_CONFIG_ADDRESS, PCI_CONFIG_DATA, and PCI_INT_ACK, are little endian registers.
13.3.1.1
Figure 13-3
The PCI_CONFIG_ADDRESS register holds the address for an access to the PCI configuration space
from the local bus. This register must be programmed before accessing PCI_CONFIG_DATA to perform
the transaction. Only 32-bit accesses are permitted.
If EN=1, BN=0, and DN=0, the access is to the internal PCI configuration registers, so no transaction is
generated on the PCI bus.
If EN=1, BN=0, DN=31, FN=7, and RN=0, writing to PCI_CONFIG_DATA generates a special cycle
transaction and reading from PCI_CONFIG_DATA generates an interrupt acknowledge transaction.
Table 13-6
Freescale Semiconductor
Offset 0x0
Reset
30–24
23–16
Bits
W EN
31
R
31
30
shows the bit settings of the PCI_CONFIG_ADDRESS register.
shows the PCI_CONFIG_ADDRESS register fields.
PCI_CONFIG_ADDRESS
MPC8313E PowerQUICC™ II Pro Integrated Processor Family Reference Manual, Rev. 2
Name
EN
BN
—
—
Enable configuration transaction. Determines the type of transaction to be generated.
0 No configuration transaction will be generated by accessing the CONFIG_DATA register. Such an
1 A configuration transaction will be generated by accessing the CONFIG_DATA register if BN and
Reserved
Bus number. Specifies the bus segment to which a configuration transaction is directed. If this field
is 0, a Type 0 configuration transaction is generated. Otherwise, a Type 1 configuration transaction
is generated.
access will be passed through to the PCI bus as an I/O transaction. Since this is generally not
desirable, the user should not access CONFIG_DATA when the EN bit is 0.
DN are not both zero.
Table 13-6. PCI_CONFIG_ADDRESS Field Descriptions
24 23
Figure 13-3. PCI_CONFIG_ADDRESS Register
BN
All zeros
16 15
Description
DN
11 10
FN
8
7
RN
Access: Write only
PCI Bus Interface
2
1
13-13
—
0
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