MPC8313EZQADDC Freescale Semiconductor, MPC8313EZQADDC Datasheet - Page 497
MPC8313EZQADDC
Manufacturer Part Number
MPC8313EZQADDC
Description
Microprocessors - MPU 8313 REV2.2 PB W/ENC
Manufacturer
Freescale Semiconductor
Datasheet
1.MPC8313CZQADDC.pdf
(1214 pages)
Specifications of MPC8313EZQADDC
Processor Series
MPC8313E
Core
e300
Data Bus Width
16 bit
Maximum Clock Frequency
133 MHz
Program Memory Size
16 KB
Data Ram Size
16 KB
Interface Type
I2C
Mounting Style
SMD/SMT
Package / Case
PBGA
Number Of Programmable I/os
32
Number Of Timers
4
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10.4.2.3
The banks selected to work with the GPCM support an option to drive the LCSn signal with different
timings (with respect to the external address/data bus). LCSn can be driven in any of the following ways:
Freescale Semiconductor
•
•
•
•
•
Simultaneous with the latched memory address. (This refers to the externally latched address and
not the address timing on LAD. That is, the chip select does not assert during LALE).
One quarter of a clock cycle later (for LCRR[CLKDIV] = 4, 8).
One half of a clock cycle later (for LCRR[CLKDIV] = 2, 4, or 8).
One clock cycle later (for LCRR[CLKDIV] = 4), when OR
Two clock cycles later (for LCRR[CLKDIV] = 2, 4, or 8), when OR
1
TRLX
Times in parentheses are specific for the case LCRR[CLKDIV] = 2; other times apply to all CLKDIV values.
Option Register Attributes
0
0
0
1
1
1
1
1
1
1
1
1
1
1
1
Chip-Select Assertion Timing
MPC8313E PowerQUICC™ II Pro Integrated Processor Family Reference Manual, Rev. 2
XACS
1
1
1
0
0
0
1
1
1
0
0
0
1
1
1
Table 10-33. GPCM Write Control Signal Timing (continued)
ACS
00
10
11
00
10
11
00
10
11
00
10
11
00
10
11
CSNT
1
1
1
0
0
0
0
0
0
1
1
1
1
1
1
t
AWCS
(1½)
(1½)
1¼
1½
1¼
1½
0
1
2
0
0
2
3
0
0
2
3
(½+2×SCY)
(½+2×SCY)
1¾+2×SCY
1½+2×SCY
1½+2×SCY
1¼+2×SCY
(2+2×SCY)
(1+2×SCY)
¾+2×SCY
¾+2×SCY
2+2×SCY
2+2×SCY
1+2×SCY
1+2×SCY
3+2×SCY
3+2×SCY
(½+SCY)
(½+SCY)
Signal Timing (LCLK clock cycles)
¾+SCY
¾+SCY
2+SCY
t
CSWP
t
AWE
1
1
2
1
2
2
1
2
3
1
2
2
1
2
3
n
[XACS] = 1.
n
t
[XACS] = 1.
WEN
1¼
1¼
(0)
(1)
(1)
¼
0
0
0
0
0
0
0
0
0
0
0
0
Enhanced Local Bus Controller
1
(2½+2×SCY)
(2½+2×SCY)
(2½+2×SCY)
(3½+2×SCY)
2¾+2×SCY
2¾+2×SCY
2¾+2×SCY
3¾+2×SCY
(1½+SCY)
(2½+SCY)
2+2×SCY
3+2×SCY
3+2×SCY
2+2×SCY
3+2×SCY
4+2×SCY
3+2×SCY
3+2×SCY
1¾+SCY
2¾+SCY
2+SCY
t
WC
10-49
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