MPC8313EZQADDC Freescale Semiconductor, MPC8313EZQADDC Datasheet - Page 1091

• Manufacturer Part Number: MPC8313EZQADDC
• Description: Microprocessors - MPU 8313 REV2.2 PB W/ENC
• Manufacturer: Freescale Semiconductor

Specifications of MPC8313EZQADDC

• Processor Series: MPC8313E
• Core: e300
• Data Bus Width: 16 bit
• Maximum Clock Frequency: 133 MHz
• Program Memory Size: 16 KB
• Data Ram Size: 16 KB
• Interface Type: I2C
• Mounting Style: SMD/SMT
• Package / Case: PBGA
• Number Of Programmable I/os: 32
• Number Of Timers: 4

17.3.1.3
Figure 17-4
Table 17-6
Freescale Semiconductor
.
Bits
0
1
2
3
4
5
6
7
Name
MSTA Master/slave mode START
BCST Broadcast
TXAK Transfer acknowledge. Specifies the value driven onto the SDA n line during acknowledge cycles for both
RSTA
MIEN
MEN
MTX
—
describes the I2CnCR bit settings.
shows the I
Offset 0x0_3008
Reset
I
MPC8313E PowerQUICC™ II Pro Integrated Processor Family Reference Manual, Rev. 2
2
C n Control Register (I2C n CR)
Module enable. Controls the software reset of the I
0 The module is reset and disabled. The interface is held in reset, but the registers can still be accessed.
1 The I
Module interrupt enable
0 Interrupts from the I
1 Interrupts from the I
0 On a transition to zero, a STOP condition is generated and the mode changes from master to slave.
1 When MSTA changes from zero to one, a START condition is generated on the bus and master mode is
Transmit/receive mode select. Selects the direction of the master and slave transfers. When configured as a
slave, this bit should be set by software according to I2C n SR[SRW]. In master mode, the bit should be set
according to the type of transfer required. Therefore, for address cycles, this bit will always high. MTX is
cleared when the master loses arbitration.
0 Receive mode
1 Transmit mode
master and slave receivers. The value of this bit applies only when the I
not a transmitter. It also does not apply to address cycles; when the device is addressed as a slave, an
acknowledge is always sent.
0 An acknowledge signal (low value on SDA n ) is sent out to the bus at the 9th clock bit after receiving one
1 No acknowledge signal response (high value on SDA n ) is sent.
Repeated START. Note that this bit is not readable, which means if a read is performed to RSTA, a zero value
is returned.
0 No START condition is generated
1 Setting this bit always generates a repeated START condition on the bus, provides the device with the
Reserved, should be cleared
0 Disables the broadcast accept capability
1 Enables the I
W
R
registers for slave receive or master START can be initialized before setting this bit.
Cleared without generating a STOP condition when the master loses arbitration.
selected.
byte of data.
current bus master. Attempting a repeated START at the wrong time (or if the bus is owned by another
master), results in loss of arbitration.
MEN
2
0
C module is enabled. MEN must be set before any other control register bits have any effect. All I
2
Cn control register.
2
C to accept broadcast messages at address zero
MIEN
Figure 17-4. I
1
Table 17-6. I2C n CR Field Descriptions
2
2
C module are disabled. This does not clear any pending interrupt conditions.
C module are enabled. An interrupt occurs provided I2C n SR[MIF] is also set.
MSTA
2
2
C n Control Register (I2C n CR)
MTX
3
All zeros
Description
2
TXAK
C module.
4
RSTA
5
2
C module is configured as a receiver,
—
6
Access: Mixed
BCST
7
I
2
C Interfaces
17-7
2
C