MPC8313EZQADDC Freescale Semiconductor, MPC8313EZQADDC Datasheet - Page 833
MPC8313EZQADDC
Manufacturer Part Number
MPC8313EZQADDC
Description
Microprocessors - MPU 8313 REV2.2 PB W/ENC
Manufacturer
Freescale Semiconductor
Datasheet
1.MPC8313CZQADDC.pdf
(1214 pages)
Specifications of MPC8313EZQADDC
Processor Series
MPC8313E
Core
e300
Data Bus Width
16 bit
Maximum Clock Frequency
133 MHz
Program Memory Size
16 KB
Data Ram Size
16 KB
Interface Type
I2C
Mounting Style
SMD/SMT
Package / Case
PBGA
Number Of Programmable I/os
32
Number Of Timers
4
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15.5.3.10.4 Timer PTP Packet Event Register (TMR_PEVENT)
The eTSEC precision timer logic can generate interrupts upon the capture of a timestamp due to either
transmission or reception of a frame. If an event occurs and its corresponding enable bit is set in the event
mask register (PEMASK), the event also causes a hardware interrupt at the PIC. A bit in the timer event
register is cleared by writing a 1 to that bit position. Figure 15-107 describes the definition for the
TMR_PEVENT register.
Table 15-113
15.5.3.10.5 Timer Event Mask Register (TMR_PEMASK)
Timer event mask register. The event mask register provides control over which possible interrupt events
in the TMR_PEVENT register are permitted to participate in generating hardware interrupts to the PIC.
All implemented bits in this register are R/W and cleared upon a hardware reset.
the definition for the TMR_PEMASK register.
Freescale Semiconductor
24–30
0–21
Bits
Offset eTSEC1:0x2_4E0C
Reset
Reset
22
23
31
W
W
R
R
16
0
Name
TXP2
TXP1
RXP
describes the fields of the TMR_PEVENT register fields for the timer.
—
—
MPC8313E PowerQUICC™ II Pro Integrated Processor Family Reference Manual, Rev. 2
Reserved
Indicates that a PTP frame has been transmitted and its timestamp is stored in TXTS2 register.
0 PTP packet not transmitted
1 PTP packet has been transmitted
Indicates that a PTP frame has been transmitted and its timestamp is stored in TXTS1 register.
0 PTP packet not transmitted
1 PTP packet has been transmitted
Reserved
Indicates that a PTP frame has been received
0 PTP packet not received
1 PTP packet has been received
Table 15-113. TMR_PEVENT Register Field Descriptions
—
Figure 15-107. TMR_PEVENT Register Definition
21
TXP2
22
All zeros
All zeros
—
TXP1
23
Description
24
Enhanced Three-Speed Ethernet Controllers
—
Figure 15-108
Access: Read/Write
30
describes
RXP
15
31
15-115
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