MPC8313EZQADDC Freescale Semiconductor, MPC8313EZQADDC Datasheet - Page 928

• Manufacturer Part Number: MPC8313EZQADDC
• Description: Microprocessors - MPU 8313 REV2.2 PB W/ENC
• Manufacturer: Freescale Semiconductor

Specifications of MPC8313EZQADDC

• Processor Series: MPC8313E
• Core: e300
• Data Bus Width: 16 bit
• Maximum Clock Frequency: 133 MHz
• Program Memory Size: 16 KB
• Data Ram Size: 16 KB
• Interface Type: I2C
• Mounting Style: SMD/SMT
• Package / Case: PBGA
• Number Of Programmable I/os: 32
• Number Of Timers: 4

Enhanced Three-Speed Ethernet Controllers
15-210
read the MII Mgmt AN Link Partner Base Page Ability register and check bits 9 and 10. (Half and Full Duplex)
MII Mgmt AN Link Partner Base Page Ability ---> [0000_0000_0000_0000_0000_000x_1110_0000]
MPC8313E PowerQUICC™ II Pro Integrated Processor Family Reference Manual, Rev. 2
Perform an MII Mgmt read cycle of AN Link Partner Base Page Ability Register. (Optional)
(Uses the PHY address (0x10) and Register address (5) placed in MIIMADD register),
Table 15-178. SGMII Mode Register Initialization Steps (continued)
RBASE0–RBASE7[LLLL_LLLL_LLLL_LLLL_LLLL_LLLL_LLLL_L000]
TBASE0–TBASE7[LLLL_LLLL_LLLL_LLLL_LLLL_LLLL_LLLL_L000]
Setup MIIMADD[0000_0000_0000_0000_0001_0000_0000_0101]
Initialize (Empty) Receive Descriptor ring and fill with empty buffers
MACnADDR1/2[0000_0000_0000_0000_0000_0000_0000_0000]
Initialize (Empty) Transmit Descriptor ring and fill buffers with Data
MACCFG1[0000_0000_0000_0000_0000_0000_0000_0101]
DMACTRL[0000_0000_0000_0000_0000_0000_0000_0000]
GADDR n [0000_0000_0000_0000_0000_0000_0000_0000]
IEVENT[0000_0000_0000_0000_0000_0000_0000_0000]
RCTRL[0000_0000_0000_0000_0000_0000_0000_0000]
IMASK[0000_0000_0000_0000_0000_0000_0000_0000]
Initialize MACnADDR1/2 (Optional)
Initialize DMACTRL (Optional)
Clear MIIMCOM[Read Cycle]
Initialize GADDR n (Optional)
Initialize RBASE0–RBASE7,
Initialize TBASE0–TBASE7,
Set MIIMCOM[Read Cycle]
When MIIMIND[BUSY] = 0,
Initialize RCTRL (Optional)
Initialize IMASK (Optional)
Enable Transmit Queues
Enable Receive Queues
Clear IEVENT register,
Enable Rx and Tx,
Initialize RQUEUE
Initialize TQUEUE
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