MPC8313EZQADDC Freescale Semiconductor, MPC8313EZQADDC Datasheet - Page 237

• Manufacturer Part Number: MPC8313EZQADDC
• Description: Microprocessors - MPU 8313 REV2.2 PB W/ENC
• Manufacturer: Freescale Semiconductor

Specifications of MPC8313EZQADDC

• Processor Series: MPC8313E
• Core: e300
• Data Bus Width: 16 bit
• Maximum Clock Frequency: 133 MHz
• Program Memory Size: 16 KB
• Data Ram Size: 16 KB
• Interface Type: I2C
• Mounting Style: SMD/SMT
• Package / Case: PBGA
• Number Of Programmable I/os: 32
• Number Of Timers: 4

5.3.2.9
Figure 5-17
1
Table 5-32
5.4
The following sections describe the theory of operation of the software watchdog timer (WDT) in the
device, including a definition of the external signals and the functions they serve. Additionally, the
configuration, control, and status registers are also described. Note that individual chapters in this book
describe specific initialization aspects for each individual block.
5.4.1
The device provides a software watchdog timer (WDT) feature to prevent system lock in case the software
becomes trapped in loops with no controlled exit. Watchdog timer operations are configured in the system
watchdog control register (SWCRR).
The watchdog counter is a free-running down-counter that generates a reset or a non-maskable interrupt
on underflow. To prevent a reset, software must periodically restart the countdown. The WDT is
responsible for asserting a hardware reset or machine-check interrupt (mcp) if the software fails to service
Freescale Semiconductor
Reset
10–31
Offset 0x0012C
Bits
Reset value of bits 0-9 depends on the actual state of the signals being monitored.
0–1
2–5
6–9
W
R
1
Name
0
0
Software Watchdog Timer (WDT)
PZ
NZ
—
—
shows the bit settings of the DDRDSR.
WDT Overview
contains the debug status bits from the DDR SDRAM controller.
—
DDR Debug Status Register (DDRDSR)
MPC8313E PowerQUICC™ II Pro Integrated Processor Family Reference Manual, Rev. 2
Reserved
Current setting of PFET driver impedance
0000 Half strength—highest Z
1000 Higher Z than nominal
1100 Nominal impedance setting
1110 Lower Z than nominal
1111 Much lower Z than nominal
Current setting of NFET driver impedance
0000 Half strength—highest Z
1000 Higher Z than nominal
1100 Nominal impedance setting
1110 Lower Z than nominal
1111 Much lower Z than nominal
Reserved
1
0
1 1 0 0 1 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
2
PZ
Figure 5-17. DDR Debug Status Register (DDRDSR)
5
6
Table 5-32. DDRDSR Field Descriptions
NZ
9 10
Description
—
System Configuration
Access: Read
5-29
31