MPC8313EZQADDC Freescale Semiconductor, MPC8313EZQADDC Datasheet - Page 228
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MPC8313EZQADDC
Manufacturer Part Number
MPC8313EZQADDC
Description
Microprocessors - MPU 8313 REV2.2 PB W/ENC
Manufacturer
Freescale Semiconductor
Datasheet
1.MPC8313CZQADDC.pdf
(1214 pages)
Specifications of MPC8313EZQADDC
Processor Series
MPC8313E
Core
e300
Data Bus Width
16 bit
Maximum Clock Frequency
133 MHz
Program Memory Size
16 KB
Data Ram Size
16 KB
Interface Type
I2C
Mounting Style
SMD/SMT
Package / Case
PBGA
Number Of Programmable I/os
32
Number Of Timers
4
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System Configuration
5-20
10–11
12–15
16–17
18–19
20–21
22–23
24-31
Bits
9
TSEC1588
TSECBDP
COREPR
TSECDP
TSECEP
Name
TBEN
—
—
MPC8313E PowerQUICC™ II Pro Integrated Processor Family Reference Manual, Rev. 2
0 Time base unit is disabled.
1 Time base unit is enabled.
from 4 possible levels.
00 Level 0 (lowest priority)
01 Level 1
10 Level 2
11 Level 3 (highest priority)
Reserved. Should be cleared.
00 Selects 1588 pins muxed with eTSEC1 (default)
01 Selects 1588 pins muxed with LA[7:15] pads.
10 Selects 1588 pins muxed with UART2 + I2C1 pads.
11 Reserved
require to transfer data on this bus. The level of priority can be chosen from 4 possible levels.
00 Level 0 (lowest priority)
01 Level 1
10 Level 2
11 Level 3 (highest priority)
when they require to transfer a buffer descriptor (BD) on this bus. The level of priority can be chosen
from 4 possible levels.
00 Level 0 (lowest priority)
01 Level 1
10 Level 2
11 Level 3 (highest priority)
emergency condition occurs. The level of priority can be chosen from 4 possible levels.
00 Level 0 (lowest priority)
01 Level 1
10 Level 2
11 Level 3 (highest priority)
Reserved, should be cleared.
e300c3 core time base unit enable
e300c3 core CSB request priority. The priority level for the core in accessing the CSB can be chosen
eTSEC data priority. Selects the CSB request priority driven by eTSEC1 and eTSEC2 when they
eTSEC buffer descriptor priority. Selects the CSB request priority driven by eTSEC1 and eTSEC2
eTSEC emergency priority. Selects the CSB request priority driven by eTSEC1 and eTSEC2 when an
CFG_RESET_SRC
0000
1000
1001
1010
1011
1100
Table 5-26. SPCR Bit Settings (continued)
Table 5-27. CFG_RESET_SRC Values
SPCR[0]
0
0
0
0
1
1
Description
SPCR[1]
0
0
1
0
0
0
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