MPC8313EZQADDC Freescale Semiconductor, MPC8313EZQADDC Datasheet - Page 1157
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MPC8313EZQADDC
Manufacturer Part Number
MPC8313EZQADDC
Description
Microprocessors - MPU 8313 REV2.2 PB W/ENC
Manufacturer
Freescale Semiconductor
Datasheet
1.MPC8313CZQADDC.pdf
(1214 pages)
Specifications of MPC8313EZQADDC
Processor Series
MPC8313E
Core
e300
Data Bus Width
16 bit
Maximum Clock Frequency
133 MHz
Program Memory Size
16 KB
Data Ram Size
16 KB
Interface Type
I2C
Mounting Style
SMD/SMT
Package / Case
PBGA
Number Of Programmable I/os
32
Number Of Timers
4
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Table 21-7
21.3.6
The GPIO interrupt control register (GPICR), shown in
corresponding port line asserts an interrupt request on either a high-to-low change or any change on the
state of the signal.
Table 21-8
Freescale Semiconductor
0–31
0–31
Bits
Bits
Offset 0xC10
Reset
Offset 0xC14
Reset
W
W
R
R
Name
Name
0
0
D n
D n
defines the bit fields of GPIMR.
defines the bit fields of GPICR.
GPIO Interrupt Control Register (GPICR)
MPC8313E PowerQUICC™ II Pro Integrated Processor Family Reference Manual, Rev. 2
Interrupt mask. Indicates whether an interrupt event is masked or not masked.
0 The input interrupt signal is masked (disabled).
1 The input interrupt signal is not masked (enabled).
Edge detection mode. The corresponding port line asserts an interrupt request according to the following:
0 Any change on the state of the port generates an interrupt request.
1 High-to-low change on the port generates an interrupt request.
Figure 21-7. GPIO Interrupt Control Register (GPICR)
Figure 21-6. GPIO Interrupt Mask Register (GPIMR)
Table 21-7. GPIMR Bit Settings
Table 21-8. GPICR Bit Settings
All zeros
All zeros
Description
Description
D n
D n
Figure
21-7, determines whether the
General Purpose I/O (GPIO)
Access: Read/write
Access: Read/write
21-5
31
31
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