MPC8313EZQADDC Freescale Semiconductor, MPC8313EZQADDC Datasheet - Page 1201
MPC8313EZQADDC
Manufacturer Part Number
MPC8313EZQADDC
Description
Microprocessors - MPU 8313 REV2.2 PB W/ENC
Manufacturer
Freescale Semiconductor
Datasheet
1.MPC8313CZQADDC.pdf
(1214 pages)
Specifications of MPC8313EZQADDC
Processor Series
MPC8313E
Core
e300
Data Bus Width
16 bit
Maximum Clock Frequency
133 MHz
Program Memory Size
16 KB
Data Ram Size
16 KB
Interface Type
I2C
Mounting Style
SMD/SMT
Package / Case
PBGA
Number Of Programmable I/os
32
Number Of Timers
4
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Index
DDR memory controller
Debug configuration, 5-26
Debug facilities, 7-38
Debug modes
Decrementer, 7-33
Descriptor structure, 14-11
DEU
DMA controller, see DMA/messaging unit, DMA controller
DMA engine, 16-46
DMA/messaging unit
Do-Complete-Split state
Doorbell registers, 12-6–12-7
Freescale Semiconductor
debug configuration, 5-26
overview, 1-10
DDR, 5-26
local bus, 5-27
performance monitor uses, 7-12
LBC source ID debug mode, 10-4
FIFOs, 14-28
interrupt control register, 14-25, 14-47
interrupt status register, 14-24, 14-45
IV register, 14-27
key registers, 14-28
key size register, 14-20, 14-21, 14-42
mode register, 14-19, 14-40
reset control register, 14-22, 14-43
block diagram, 12-1
DMA controller
features, 12-1
functional description, 12-15
initialization steps
memory map/register definition, 12-2
message unit, 12-15
registers, 12-3–12-15
asynchronous, 16-91
periodic interrupt, 16-100
block diagram, 12-16
descriptors, 12-18
halt and error conditions, 12-17
operation, 12-16
overview, 1-17, 12-16
in chaining mode, 12-20
in direct mode, 12-20
doorbell registers, 12-16
messaging registers, 12-15
by acronym, see Register Index
configuration, control, and status registers, 12-3–12-9
big-endian mode, 12-19
DMA chain, 12-19
little-endian mode, 12-20
coherency, 12-17
MPC8313E PowerQUICC™ II Pro Integrated Processor Reference Manual, Rev. 2
Do-Start-Split state
DSI (data storage interrupt), 7-32
DTLB, 7-3
Dual universal asynchronous receiver/transmitters, see
DUART
Dynamic power management enable, 7-21
asynchronous, 16-91
periodic interrupt, 16-99
asynchronous communication bits, 18-2
baud-rate generator logic, 18-20
block diagram, 18-2
divisor latch access bit (ULCRn[DLAB]), 18-4, 18-11
error handling, 18-21
features, 18-2
functional description, 18-18
initialization/application information, 18-22
interrupt handling
memory map/register definition, 18-4–18-5
modes of operation, 18-3
overview, 18-1
PC16450 UART compatibility, 18-2
registers, 18-5–18-18
serial interface data format, 18-2
serial interface operation, 18-19–18-20
signals, 18-3–18-4
DUART
parity bit, 18-19
START bit, 18-19
STOP bit, 18-20
framing error, 18-9, 18-14, 18-19, 18-20, 18-21
overrun error, 18-21
parity error, 18-21
interrupt control logic, 18-22
interrupt enable and control registers, 18-8–18-10
DMA mode selection, 18-22
FIFO mode, 18-21
local loop-back mode, 18-20
by acronym, see Register Index
data transfer, 18-19
START bit, 18-19
STOP bit, 18-20
transaction protocol example, 18-19
UART_CTS[0:1] (DUART clear to send), 18-1, 18-3,
UART_RTS[0:1] (DUART request to send), 18-1, 18-3,
UART_SIN [0:1] (DUART transmitter serial data in),
UART_SOUT [0:1] (DUART transmitter serial data
interrupts, 18-21
18-4
18-4
18-3
out), 18-3, 18-4
Index-3
D–D
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