ADP1046DC1-EVALZ Analog Devices, ADP1046DC1-EVALZ Datasheet - Page 51

• Manufacturer Part Number: ADP1046DC1-EVALZ
• Description: Daughter Cards & OEM Boards ADP1046 Daughter Card
• Manufacturer: Analog Devices
• Series: ADP1046r

Specifications of ADP1046DC1-EVALZ

• Rohs: yes
• Product: Daughter Cards
• Description/function: 100 kHz daughter board
• Interface Type: I2C
• Maximum Operating Temperature: + 125 C
• Minimum Operating Temperature: - 40 C
• Operating Supply Voltage: 3.3 V
• Factory Pack Quantity: 1
• For Use With: ADP1046

Data Sheet
Register 0x08 to Register 0x0D allow the user to program the response when each flag is set.
Table 13. Register 0x08 to Register 0x0D—Fault Configuration Register Bit Descriptions
Bits
7
[6:4]
3
[2:0]
Table 14. Register 0x0E—Flag Configuration Register
Bits
7
6
5
[4:2]
[1:0]
Bit Name
VDD OV/VCORE OV
flags ignore
VDD OV/VCORE OV
restart
VDD OV/VCORE OV
debounce
Accurate OCP debounce
for CS1 and CS2
Power supply reenable
time
Bit Name
Timing
Action
Timing
Action
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Description
This bit specifies when the flag is set.
0 = after debounce.
1 = immediately.
These bits specify the action that the part takes in response to the flag.
Bit 6
0
0
0
0
1
1
1
1
Same as Bit 7.
Same as Bits[6:4].
Description
Setting this bit to 1 means that the VDD OV and VCORE OV flags are ignored.
This bit specifies whether the part downloads the EEPROM contents before it restarts.
1 = if the part shuts down, it downloads the EEPROM contents again before restarting.
0 = if the part shuts down, it does not download the EEPROM contents again before restarting.
Setting this bit to 1 means that there is a 500 μs debounce before the part shuts down. Setting
this bit to 0 means that there is a 2 μs debounce before the part shuts down.
When an accurate OCP flag is set, there is a debounce time before the flag action is performed.
These bits set the flag debounce time. The ADC sampling rate adds a variable latency from
2.62 ms to 5.24 ms to this debounce time.
Bit 4
0
0
0
0
1
1
1
1
These bits specify the time delay before restarting the power supply after a shutdown.
SR1, SR2, and OrFET are reenabled immediately.
Bit 1
0
0
1
1
Bit 5
0
0
1
1
0
0
1
1
Bit 3
0
0
1
1
0
0
1
1
Bit 0
0
1
0
1
Rev. B | Page 51 of 92
Bit 4
0
1
0
1
0
1
0
1
Bit 2
0
1
0
1
0
1
0
1
Time (sec)
0.5
1
2
4
Debounce
2.6 ms
9.8 ms
130 ms
260 ms
600 ms
1.3 sec
2 sec
2.6 sec
Action
Ignore flag completely
Disable SR1 and SR2
Disable OrFET
Disable the power supply and reenable it after the power
supply reenable time set in Register 0x0E[1:0]
Disable OUTAUX
Disable all PWM outputs except OUTAUX
Disable SR1, SR2, and OrFET
Disable the power supply and keep it disabled; PSON
signal is necessary to restart
ADP1046