ADP1046DC1-EVALZ Analog Devices, ADP1046DC1-EVALZ Datasheet - Page 68

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ADP1046DC1-EVALZ

Manufacturer Part Number
ADP1046DC1-EVALZ
Description
Daughter Cards & OEM Boards ADP1046 Daughter Card
Manufacturer
Analog Devices
Series
ADP1046r
Datasheet

Specifications of ADP1046DC1-EVALZ

Rohs
yes
Product
Daughter Cards
Description/function
100 kHz daughter board
Interface Type
I2C
Maximum Operating Temperature
+ 125 C
Minimum Operating Temperature
- 40 C
Operating Supply Voltage
3.3 V
Factory Pack Quantity
1
For Use With
ADP1046
Bits
[5:0]
Table 65. Register 0x41—OUTA Rising Edge Timing (OUTA Pin)
Bits
[7:0]
Table 66. Register 0x42—OUTA Rising Edge Setting (OUTA Pin)
Bits
[7:4]
3
2
1
0
Table 67. Register 0x43—OUTA Falling Edge Timing (OUTA Pin)
Bits
[7:0]
Table 68. Register 0x44—OUTA Falling Edge Setting (OUTA Pin)
Bits
[7:4]
3
2
[1:0]
ADP1046
Bit Name
Switching frequency
Bit Name
t
Bit Name
t
Modulate enable
t
Reserved
Volt-second balance
source selection
Bit Name
t
Bit Name
t
Modulate enable
t
Reserved
1
1
1
2
2
2
sign
sign
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Description
Bit 5
1
1
1
1
1
1
1
Description
This register contains the eight MSBs of the 12-bit t
four bits of Register 0x42, which contains the four LSBs of the t
5 ns resolution. The entire switching period is divided into 40 ns time steps. If the t_rise and
t_fall of a PWM edge occur within the same 40 ns time step, the PWM output is 0 V. If the t_rise
and t_fall occur in different 40 ns time steps, the PWM output is set to the programmed value.
The absolute maximum pulse width is t
Description
These bits contain the four LSBs of the 12-bit t
bits of Register 0x41, which contains the eight MSBs of the t
5 ns resolution. The entire switching period is divided into 40 ns time steps. If the t_rise and
t_fall of a PWM edge occur within the same 40 ns time step, the PWM output is 0 V. If the t_rise
and t_fall occur in different 40 ns time steps, the PWM output is set to the programmed value.
The absolute maximum pulse width is t
1 = PWM modulation acts on the t
0 = no PWM modulation of the t
1 = negative sign. Increase of PWM modulation moves t
0 = positive sign. Increase of PWM modulation moves t
Reserved.
If this bit is set to 1, the OUTA rising edge is selected as the start of the integration period for
volt-second balance.
Description
This register contains the eight MSBs of the 12-bit t
four bits of Register 0x44, which contains the four LSBs of the t
5 ns resolution. The entire switching period is divided into 40 ns time steps. If the t_rise and
t_fall of a PWM edge occur within the same 40 ns time step, the PWM output is 0 V. If the t_rise
and t_fall occur in different 40 ns time steps, the PWM output is set to the programmed value.
The absolute maximum pulse width is t
Description
These bits contain the four LSBs of the 12-bit t
bits of Register 0x43, which contains the eight MSBs of the t
5 ns resolution. The entire switching period is divided into 40 ns time steps. If the t_rise and
t_fall of a PWM edge occur within the same 40 ns time step, the PWM output is 0 V. If the t_rise
and t_fall occur in different 40 ns time steps, the PWM output is set to the programmed value.
The absolute maximum pulse width is t
1 = PWM modulation acts on the t
0 = no PWM modulation of the t
1 = negative sign. Increase of PWM modulation moves t
0 = positive sign. Increase of PWM modulation moves t
Reserved.
Bit 4
1
1
1
1
1
1
1
Rev. B | Page 68 of 92
Bit 3
0
0
0
0
0
0
1
1
2
edge.
edge.
Bit 2
0
0
0
1
1
1
1
1
2
edge.
edge.
PERIOD
PERIOD
PERIOD
PERIOD
− 5 ns.
− 5 ns.
− 5 ns.
− 5 ns.
Bit 1
0
1
1
0
0
1
1
1
2
time. This value is always used with the eight
time. This value is always used with the eight
1
2
time. This value is always used with the top
time. This value is always used with the top
1
2
1
2
left.
left.
Bit 0
1
0
1
0
1
0
1
right.
right.
1
2
time. Each LSB corresponds to
time. Each LSB corresponds to
1
2
time. Each LSB corresponds to
time. Each LSB corresponds to
Frequency (kHz)
416.67
446.43
480.77
520.83
568.18
625
Resonant mode
Data Sheet

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