ADP1046DC1-EVALZ Analog Devices, ADP1046DC1-EVALZ Datasheet - Page 76

• Manufacturer Part Number: ADP1046DC1-EVALZ
• Description: Daughter Cards & OEM Boards ADP1046 Daughter Card
• Manufacturer: Analog Devices
• Series: ADP1046r

Specifications of ADP1046DC1-EVALZ

• Rohs: yes
• Product: Daughter Cards
• Description/function: 100 kHz daughter board
• Interface Type: I2C
• Maximum Operating Temperature: + 125 C
• Minimum Operating Temperature: - 40 C
• Operating Supply Voltage: 3.3 V
• Factory Pack Quantity: 1
• For Use With: ADP1046

Bits
[2:0]
Table 96. Register 0x60—Normal Mode Digital Filter LF Gain Setting
Bits
[7:0]
Table 97. Register 0x61—Normal Mode Digital Filter Zero Setting
Bits
[7:0]
Table 98. Register 0x62—Normal Mode Digital Filter Pole Setting
Bits
[7:0]
Table 99. Register 0x63—Normal Mode Digital Filter HF Gain Setting
Bits
[7:0]
Table 100. Register 0x64—Light Load Mode Digital Filter LF Gain Setting
Bits
[7:0]
Table 101. Register 0x65—Light Load Mode Digital Filter Zero Setting
Bits
[7:0]
Table 102. Register 0x66—Light Load Mode Digital Filter Pole Setting
Bits
[7:0]
Table 103. Register 0x67—Light Load Mode Digital Filter HF Gain Setting
Bits
[7:0]
ADP1046
Bit Name
Slew rate
Bit Name
LF gain setting
Bit Name
Zero setting
Bit Name
Pole location
Bit Name
HF gain setting
Bit Name
LF gain setting
Bit Name
Zero setting
Bit Name
Pole location
Bit Name
HF gain setting
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Description
These bits specify the slew rate at the VS3± pins for the change in the voltage reference setting.
Bit 2
0
0
0
0
1
1
1
1
Description
This register determines the low frequency gain of the loop response. Programmable over a 20 dB
range. Each LSB corresponds to a 0.3 dB increase. See Figure 57.
Description
This register determines the position of the final zero. See Figure 57.
Description
This register determines the position of the final pole. See Figure 57.
Description
This register determines the high frequency gain of the loop response. Programmable over a 20 dB
range. Each LSB corresponds to a 0.3 dB increase. See Figure 57.
Description
This register determines the low frequency gain of the loop response. Programmable over a 20 dB
range. Each LSB corresponds to a 0.3 dB increase. See Figure 57.
Description
This register determines the position of the final zero. See Figure 57.
Description
This register determines the position of the final pole. See Figure 57.
Description
This register determines the high frequency gain of the loop response. Programmable over a 20 dB
range. Each LSB corresponds to a 0.3 dB increase. See Figure 57.
Bit 1
0
0
1
1
0
0
1
1
Bit 0
0
1
0
1
0
1
0
1
Rev. B | Page 76 of 92
Slew Rate
200 mV/ms
100 mV/ms
50 mV/ms
25 mV/ms
12.5 mV/ms
6.25 mV/ms
3.125 mV/ms
1.5625 mV/ms (4 LSB/ms)
Data Sheet