ADP1046DC1-EVALZ Analog Devices, ADP1046DC1-EVALZ Datasheet - Page 75

• Manufacturer Part Number: ADP1046DC1-EVALZ
• Description: Daughter Cards & OEM Boards ADP1046 Daughter Card
• Manufacturer: Analog Devices
• Series: ADP1046r

Specifications of ADP1046DC1-EVALZ

• Rohs: yes
• Product: Daughter Cards
• Description/function: 100 kHz daughter board
• Interface Type: I2C
• Maximum Operating Temperature: + 125 C
• Minimum Operating Temperature: - 40 C
• Operating Supply Voltage: 3.3 V
• Factory Pack Quantity: 1
• For Use With: ADP1046

Data Sheet
Table 93. Register 0x5D—OUTx and SRx Pin Disable Settings
Bits
7
6
5
4
3
2
1
0
Table 94. Register 0x5E—ACSNS Gain Trim
Bits
7
[6:0]
DIGITAL FILTER PROGRAMMING REGISTERS
Register 0x5F to Register 0x67 can be used to program the digital filters. It is recommended that the software GUI be used to program the
digital filters.
Table 95. Register 0x5F—Soft Start and Output Voltage Slew Rate Settings
Bits
[7:5]
4
3
Bit Name
OUTAUX disable
SR2 disable
SR1 disable
OUTD disable
OUTC disable
OUTB disable
OUTA disable
GATE disable
Bit Name
Gain polarity
ACSNS gain trim
Bit Name
Soft start ramp
Soft start from
precharge
Reserved
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
100Hz
Description
Setting this bit disables the OUTAUX output.
Setting this bit disables the SR2 output.
Setting this bit disables the SR1 output.
Setting this bit disables the OUTD output.
Setting this bit disables the OUTC output.
Setting this bit disables the OUTB output.
Setting this bit disables the OUTA output.
Setting this bit disables the GATE output but does not affect the VSx feedback point.
Description
1 = negative gain is introduced.
0 = positive gain is introduced.
These bits set the gain trim for the ACSNS ADC.
Description
These bits determine the duration of the soft start ramp.
Bit 7
0
0
0
0
1
1
1
1
Setting this bit to 1 enables the soft start from precharge function. When this function is enabled,
the soft start ramp starts from the value of the voltage detected on VS1 or VS3± (depending on
the OrFET status).
Reserved.
Bit 6
0
0
1
1
0
0
1
1
Figure 57. Digital Filter Programmability
500Hz
Bit 5
0
1
0
1
0
1
0
1
Rev. B | Page 75 of 92
POLE LOCATION RANGE
1kHz
Ramp Duration
5 ms
10 ms
15 ms
20 ms
40 ms
50 ms
80 ms
100 ms
ZERO
POLE
5kHz
10kHz
ADP1046