ADP1046DC1-EVALZ Analog Devices, ADP1046DC1-EVALZ Datasheet - Page 79

• Manufacturer Part Number: ADP1046DC1-EVALZ
• Description: Daughter Cards & OEM Boards ADP1046 Daughter Card
• Manufacturer: Analog Devices
• Series: ADP1046r

Specifications of ADP1046DC1-EVALZ

• Rohs: yes
• Product: Daughter Cards
• Description/function: 100 kHz daughter board
• Interface Type: I2C
• Maximum Operating Temperature: + 125 C
• Minimum Operating Temperature: - 40 C
• Operating Supply Voltage: 3.3 V
• Factory Pack Quantity: 1
• For Use With: ADP1046

Data Sheet
Table 119. Register 0x77—Volt-Second Balance Settings (OUTC and OUTD Pins)
Bits
7
6
5
4
3
2
1
0
Table 120. Register 0x78—Volt-Second Balance Settings (SR1 and SR2 Pins)
Bits
7
6
5
4
3
2
1
0
Table 121. Register 0x79—SR Delay Compensation
Bits
[7:6]
[5:0]
Bit Name
Modulate enable, t
t
Modulate enable, t
t
Modulate enable, t
t
Modulate enable, t
t
Bit Name
Modulate enable, t
t
Modulate enable, t
t
Modulate enable, t
t
Modulate enable, t
t
Bit Name
Reserved
SR driver delay
5
6
7
8
9
10
11
12
sign
sign
sign
sign
sign
sign
sign
sign
5
6
7
8
9
10
11
12
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Description
Setting this bit enables modulation from balance control on the OUTC rising edge, t
recommended to allow volt-second balance on edges that are between 0 ns to 640 ns of the
switching period.
0 = positive sign. Increase of balance control modulation moves t
1 = negative sign. Increase of balance control modulation moves t
Setting this bit enables modulation from balance control on the OUTC falling edge, t
recommended to allow volt-second balance on edges that are between 0 ns to 640 ns of the
switching period.
0 = positive sign. Increase of balance control modulation moves t
1 = negative sign. Increase of balance control modulation moves t
Setting this bit enables modulation from balance control on the OUTD rising edge, t
recommended to allow volt-second balance on edges that are between 0 ns to 640 ns of the
switching period.
0 = positive sign. Increase of balance control modulation moves t
1 = negative sign. Increase of balance control modulation moves t
Setting this bit enables modulation from balance control on the OUTD falling edge, t
recommended to allow volt-second balance on edges that are between 0 ns to 640 ns of the
switching period.
0 = positive sign. Increase of balance control modulation moves t
1 = negative sign. Increase of balance control modulation moves t
Description
Setting this bit enables modulation from balance control on the SR1 rising edge, t
recommended to allow volt-second balance on edges that are between 0 ns to 640 ns of the
switching period.
0 = positive sign. Increase of balance control modulation moves t
1 = negative sign. Increase of balance control modulation moves t
Setting this bit enables modulation from balance control on the SR1 falling edge, t
recommended to allow volt-second balance on edges that are between 0 ns to 640 ns of the
switching period.
0 = positive sign. Increase of balance control modulation moves t
1 = negative sign. Increase of balance control modulation moves t
Setting this bit enables modulation from balance control on the SR2 rising edge, t
recommended to allow volt-sec balance on edges that are between 0 ns to 640 ns of the
switching period.
0 = positive sign. Increase of balance control modulation moves t
1 = negative sign. Increase of balance control modulation moves t
Setting this bit enables modulation from balance control on the SR2 falling edge, t
recommended to allow volt-second balance on edges that are between 0 ns to 640 ns of the
switching period.
0 = positive sign. Increase of balance control modulation moves t
1 = negative sign. Increase of balance control modulation moves t
Description
Reserved.
These bits specify the 6-bit representation of the SR delay in steps of 5 ns.
000000 = 0 ns.
111111 = 63 ns × 5 ns = 315 ns.
Rev. B | Page 79 of 92
5
6
7
8
9
10
11
12
5
6
7
8
9
10
11
12
right.
right.
right.
right.
right.
left.
left.
left.
left.
left.
right.
right.
right.
left.
left.
left.
ADP1046
9
11
. It is not
10
12
. It is not
5
. It is not
. It is not
7
6
. It is not
8
. It is not
. It is not
. It is not