ADP1046DC1-EVALZ Analog Devices, ADP1046DC1-EVALZ Datasheet - Page 69

• Manufacturer Part Number: ADP1046DC1-EVALZ
• Description: Daughter Cards & OEM Boards ADP1046 Daughter Card
• Manufacturer: Analog Devices
• Series: ADP1046r

Specifications of ADP1046DC1-EVALZ

• Rohs: yes
• Product: Daughter Cards
• Description/function: 100 kHz daughter board
• Interface Type: I2C
• Maximum Operating Temperature: + 125 C
• Minimum Operating Temperature: - 40 C
• Operating Supply Voltage: 3.3 V
• Factory Pack Quantity: 1
• For Use With: ADP1046

Data Sheet
Table 69. Register 0x45—OUTB Rising Edge Timing (OUTB Pin)
Bits
[7:0]
Table 70. Register 0x46—OUTB Rising Edge Setting (OUTB Pin)
Bits
[7:4]
3
2
1
0
Table 71. Register 0x47—OUTB Falling Edge Timing (OUTB Pin)
Bits
[7:0]
Table 72. Register 0x48—OUTB Falling Edge Setting (OUTB Pin)
Bits
[7:4]
3
2
[1:0]
Table 73. Register 0x49—OUTC Rising Edge Timing (OUTC Pin)
Bits
[7:0]
Bit Name
t
Bit Name
t
Modulate enable
t
Reserved
Volt-second balance
source selection
Bit Name
t
Bit Name
t
Modulate enable
t
Reserved
Bit Name
t
3
3
3
4
4
4
5
sign
sign
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Description
This register contains the eight MSBs of the 12-bit t
four bits of Register 0x46, which contains the four LSBs of the t
5 ns resolution. The entire switching period is divided into 40 ns time steps. If the t_rise and
t_fall of a PWM edge occur within the same 40 ns time step, the PWM output is 0 V. If the t_rise
and t_fall occur in different 40 ns time steps, the PWM output is set to the programmed value.
The absolute maximum pulse width is t
Description
These bits contain the four LSBs of the 12-bit t
bits of Register 0x45, which contains the eight MSBs of the t
5 ns resolution. The entire switching period is divided into 40 ns time steps. If the t_rise and
t_fall of a PWM edge occur within the same 40 ns time step, the PWM output is 0 V. If the t_rise
and t_fall occur in different 40 ns time steps, the PWM output is set to the programmed value.
The absolute maximum pulse width is t
1 = PWM modulation acts on the t
0 = no PWM modulation of the t
1 = negative sign. Increase of PWM modulation moves t
0 = positive sign. Increase of PWM modulation moves t
Reserved.
If this bit is set to 1, the OUTB rising edge is selected as the start of the integration period for
volt-second balance.
Description
This register contains the eight MSBs of the 12-bit t
four bits of Register 0x48, which contains the four LSBs of the t
5 ns resolution. The entire switching period is divided into 40 ns time steps. If the t_rise and
t_fall of a PWM edge occur within the same 40 ns time step, the PWM output is 0 V. If the t_rise
and t_fall occur in different 40 ns time steps, the PWM output is set to the programmed value.
The absolute maximum pulse width is t
Description
These bits contain the four LSBs of the 12-bit t
bits of Register 0x47, which contains the eight MSBs of the t
5 ns resolution. The entire switching period is divided into 40 ns time steps. If the t_rise and
t_fall of a PWM edge occur within the same 40 ns time step, the PWM output is 0 V. If the t_rise
and t_fall occur in different 40 ns time steps, the PWM output is set to the programmed value.
The absolute maximum pulse width is t
1 = PWM modulation acts on the t
0 = no PWM modulation of the t
1 = negative sign. Increase of PWM modulation moves t
0 = positive sign. Increase of PWM modulation moves t
Reserved.
Description
This register contains the eight MSBs of the 12-bit t
four bits of Register 0x4A, which contains the four LSBs of the t
5 ns resolution. The entire switching period is divided into 40 ns time steps. If the t_rise and
t_fall of a PWM edge occur within the same 40 ns time step, the PWM output is 0 V. If the t_rise
and t_fall occur in different 40 ns time steps, the PWM output is set to the programmed value.
The absolute maximum pulse width is t
Rev. B | Page 69 of 92
3
4
edge.
edge.
3
4
edge.
edge.
PERIOD
PERIOD
PERIOD
PERIOD
PERIOD
− 5 ns.
− 5 ns.
− 5 ns.
− 5 ns.
− 5 ns.
3
4
time. This value is always used with the eight
time. This value is always used with the eight
3
4
5
time. This value is always used with the top
time. This value is always used with the top
time. This value is always used with the top
3
4
3
4
left.
left.
right.
right.
3
4
time. Each LSB corresponds to
time. Each LSB corresponds to
3
4
5
time. Each LSB corresponds to
time. Each LSB corresponds to
time. Each LSB corresponds to
ADP1046