ADP1046DC1-EVALZ Analog Devices, ADP1046DC1-EVALZ Datasheet - Page 56

• Manufacturer Part Number: ADP1046DC1-EVALZ
• Description: Daughter Cards & OEM Boards ADP1046 Daughter Card
• Manufacturer: Analog Devices
• Series: ADP1046r

Specifications of ADP1046DC1-EVALZ

• Rohs: yes
• Product: Daughter Cards
• Description/function: 100 kHz daughter board
• Interface Type: I2C
• Maximum Operating Temperature: + 125 C
• Minimum Operating Temperature: - 40 C
• Operating Supply Voltage: 3.3 V
• Factory Pack Quantity: 1
• For Use With: ADP1046

Table 37. Register 0x25—CS2 Digital Offset Trim
Bits
[7:0]
Table 38. Register 0x26—CS2 Accurate OCP Limit
Bits
[7:0]
Table 39. Register 0x27—CS1/CS2 Fast OCP Settings
Bits
[7:6]
5
4
3
2
[1:0]
Table 40. Register 0x28—Volt-Second Balance Settings
Bits
7
6
5
4
3
ADP1046
Bit Name
CS2 digital offset trim
Bit Name
CS2 accurate OCP
Bit Name
CS1 fast OCP debounce
CS2 nominal voltage
drop
CS1 fast OCP bypass
Constant current mode
CS2 current sensing
CS1 fast OCP timeout
Bit Name
Reserved
Volt-second balance
enable
Volt-second balance
leading edge blanking
Volt-second disable
during soft start
50% blanking of each
phase
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Description
This register contains the CS2 digital trim level. This value is used to calibrate the CS2 value
that is read in Register 0x18. See the CS2 Trim section for more information.
Description
This register sets the CS2 accurate OCP current level. This 8-bit number is compared to the CS2 value
register (Register 0x18). When the CS2 value register is greater than the value in this register,
the CS2 accurate OCP flag is set. The following equation gives the CS2 accurate OCP threshold:
CS2_OCP_Threshold = CS2_OCP_Limit × (ADC_Range)/256 + 16 × (ADC_Range)/2
Description
These bits set the CS1 fast OCP debounce value. This is the minimum time that the CS1 signal
must be constantly above the fast OCP limit before the PWM outputs are shut down. When this
happens, all PWM outputs are disabled for the remainder of the switching cycle.
Bit 7
0
0
1
1
These bits set the nominal full-scale voltage drop across the sense resistor. See the CS2 Trim
section for more information. These bits set the LSB step size of the CS2 ADC.
Bit 5
0
1
Setting this bit to 1 means that the FLAGIN pin is used for CS1 fast OCP instead of the CS1 pin.
When this bit is set, constant current mode is enabled to 97% of the CS2 accurate OCP limit.
1 = constant current mode enabled.
0 = constant current mode disabled.
This bit is set high if high-side current sensing is used. This bit is set low if low-side current
sensing is used. See the CS2 Trim section for more information.
If the CS1 fast OCP comparator is set, all PWM outputs that are on at that time are immediately
disabled for the remainder of the switching cycle. The PWM outputs resume normal operation at
the beginning of the next switching cycle. These bits set the number of consecutive switching
cycles for the comparator before the CS1 fast OCP response is activated.
Bit 1
0
0
1
1
Description
Reserved.
Setting this bit enables volt-second balance for the main transformer (used for full-bridge
configurations). For more information, see the Volt-Second Balance section.
Setting this bit means that CS1 is blanked for volt-second balance calculations at the rising
edge of the PWM outputs that are selected for volt-second balance. The blanking value is the
same value configured for CS1 fast OCP blanking in Register 0x22[7:5].
0 = do not blank volt-second balance control during soft start.
1 = blank volt-second balance control during soft start.
Setting this bit limits the sampling period for the current on CS1 to less than 50% of a half cycle.
Bit 6
0
1
0
1
ADC Range (mV)
60
120
Bit 0
0
1
0
1
Rev. B | Page 56 of 92
Debounce (ns)
0
40
80
120
Number of Switching Cycles
1
62
188
440
LSB Step Size (μV)
14.65
29.30
Data Sheet
12