CDB5376 Cirrus Logic Inc, CDB5376 Datasheet - Page 75

• Manufacturer Part Number: CDB5376
• Description: EVALUATION BOARD FOR CS5376
• Manufacturer: Cirrus Logic Inc

Specifications of CDB5376

• Main Purpose: Seismic Evaluation System
• Embedded: Yes, MCU, 8-Bit
• Utilized Ic / Part: CS3301A, CS3302A, CS4373A, CS5372A, CS5376A
• Primary Attributes: Quad Digital Filter
• Secondary Attributes: Graphical User Interface, SPI™ & USB Interfaces
• Processor To Be Evaluated: CS330x, CS4373A, CS537x
• Interface Type: USB
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant, Contains lead / RoHS non-compliant
• Other names: 598-1778

CS5376A
TRST
TAP
TDO
TMS
Controller
TCK
TDI
Boundary Scan Cells
Figure 40. JTAG Block Diagram
21.BOUNDARY SCAN JTAG
The CS5376A includes an IEEE 1149.1 boundary scan JTAG port to test PCB interconnections. Refer to
the IEEE 1149.1 specification for more information about boundary scan testing.
21.1 Pin Descriptions
TRST - Pin 1
Reset input for the test access port (TAP) controller and all boundary scan cells, active low. Connect to
GND to disable the JTAG port.
TMS - Pin 2
Serial input to select the JTAG test mode.
TCK - Pin 3
Clock input to the TAP controller.
TDI - Pin 4
Serial input to the scan chain or TAP controller.
TDO - Pin 5
Serial output from the scan chain or TAP controller.
21.2 JTAG Architecture
The JTAG test circuitry consists of a test access port (TAP) controller and boundary scan cells connected
to each pin. The boundary scan cells are linked together to create a scan chain around the CS5376A.
DS612F4
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