HD64F3067RF20 Renesas Electronics America, HD64F3067RF20 Datasheet - Page 11

• Manufacturer Part Number: HD64F3067RF20
• Description: IC H8 MCU FLASH 128K 100-QFP
• Manufacturer: Renesas Electronics America
• Series: H8® H8/300Hr

Specifications of HD64F3067RF20

• Core Processor: H8/300H
• Core Size: 16-Bit
• Speed: 20MHz
• Connectivity: SCI, SmartCard
• Peripherals: DMA, PWM, WDT
• Number Of I /o: 70
• Program Memory Size: 128KB (128K x 8)
• Program Memory Type: FLASH
• Ram Size: 4K x 8
• Voltage - Supply (vcc/vdd): 4.5 V ~ 5.5 V
• Data Converters: A/D 8x10b; D/A 2x8b
• Oscillator Type: Internal
• Operating Temperature: -20°C ~ 75°C
• Package / Case: 100-QFP
• Package: 100PQFP
• Family Name: H8
• Maximum Speed: 20 MHz
• Operating Supply Voltage: 5 V
• Data Bus Width: 16|32 Bit
• Number Of Programmable I/os: 70
• Interface Type: SCI
• On-chip Adc: 8-chx10-bit
• On-chip Dac: 2-chx8-bit
• Number Of Timers: 7
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Eeprom Size: -

Section 5 Interrupt Controller
5.1
5.2
5.3
5.4
5.5
Section 6 Bus Controller
6.1
6.2
Overview........................................................................................................................... 91
5.1.1
5.1.2
5.1.3
5.1.4
Register Descriptions ........................................................................................................ 94
5.2.1
5.2.2
5.2.3
5.2.4
5.2.5
Interrupt Sources............................................................................................................... 105
5.3.1
5.3.2
5.3.3
Interrupt Operation............................................................................................................ 110
5.4.1
5.4.2
5.4.3
Usage Notes ...................................................................................................................... 117
5.5.1
5.5.2
5.5.3
Overview........................................................................................................................... 119
6.1.1
6.1.2
6.1.3
6.1.4
Register Descriptions ........................................................................................................ 124
6.2.1
6.2.2
6.2.3
6.2.4
6.2.5
6.2.6
6.2.7
6.2.8
6.2.9
Features................................................................................................................ 91
Block Diagram ..................................................................................................... 92
Pin Configuration................................................................................................. 93
Register Configuration......................................................................................... 93
System Control Register (SYSCR) ...................................................................... 94
Interrupt Priority Registers A and B (IPRA, IPRB)............................................. 95
IRQ Status Register (ISR).................................................................................... 102
IRQ Enable Register (IER) .................................................................................. 103
IRQ Sense Control Register (ISCR) .................................................................... 104
External Interrupts ............................................................................................... 105
Internal Interrupts................................................................................................. 106
Interrupt Vector Table.......................................................................................... 106
Interrupt Handling Process................................................................................... 110
Interrupt Sequence ............................................................................................... 115
Interrupt Response Time...................................................................................... 116
Contention between Interrupt and Interrupt-Disabling Instruction ...................... 117
Instructions that Inhibit Interrupts........................................................................ 118
Interrupts during EEPMOV Instruction Execution.............................................. 118
Features................................................................................................................ 119
Block Diagram ..................................................................................................... 121
Pin Configuration................................................................................................. 122
Register Configuration......................................................................................... 123
Bus Width Control Register (ABWCR)............................................................... 124
Access State Control Register (ASTCR) ............................................................. 125
Wait Control Registers H and L (WCRH, WCRL).............................................. 125
Bus Release Control Register (BRCR) ................................................................ 130
Bus Control Register (BCR) ................................................................................ 132
Chip Select Control Register (CSCR).................................................................. 134
DRAM Control Register A (DRCRA) ................................................................. 135
DRAM Control Register B (DRCRB) ................................................................. 137
Refresh Timer Control/Status Register (RTMCSR) ............................................ 140
................................................................................................... 119
.......................................................................................... 91
Rev. 4.00 Jan 26, 2006 page ix of xxii