HD64F3067RF20 Renesas Electronics America, HD64F3067RF20 Datasheet - Page 652

• Manufacturer Part Number: HD64F3067RF20
• Description: IC H8 MCU FLASH 128K 100-QFP
• Manufacturer: Renesas Electronics America
• Series: H8® H8/300Hr

Specifications of HD64F3067RF20

• Core Processor: H8/300H
• Core Size: 16-Bit
• Speed: 20MHz
• Connectivity: SCI, SmartCard
• Peripherals: DMA, PWM, WDT
• Number Of I /o: 70
• Program Memory Size: 128KB (128K x 8)
• Program Memory Type: FLASH
• Ram Size: 4K x 8
• Voltage - Supply (vcc/vdd): 4.5 V ~ 5.5 V
• Data Converters: A/D 8x10b; D/A 2x8b
• Oscillator Type: Internal
• Operating Temperature: -20°C ~ 75°C
• Package / Case: 100-QFP
• Package: 100PQFP
• Family Name: H8
• Maximum Speed: 20 MHz
• Operating Supply Voltage: 5 V
• Data Bus Width: 16|32 Bit
• Number Of Programmable I/os: 70
• Interface Type: SCI
• On-chip Adc: 8-chx10-bit
• On-chip Dac: 2-chx8-bit
• Number Of Timers: 7
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Eeprom Size: -

Section 18 ROM
(5) This LSI terminates transmit and receive operations by the on-chip SCI(channel 1) (by clearing
(6) Transition to the boot mode executes a reset-start of this LSI after setting the MD0 to MD2 and
(7) If the mode pin and FWE pin input levels are changed from 0 V to V
Notes: 1. The mode pin and FWE pin input must satisfy the mode programming setup time (t
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the RE and TE bits in serial control register (SCR)) before branching to the user program.
However, the adjusted bit rate is held in the bit rate register (BRR). At this time, the TXD
is in the high level output state (P9DDR P9
Before branching to the user program the value of the general registers in the CPU are also
undefined. Therefore, the general registers must be initialized immediately after control
branches to the user program. Since the stack pointer (SP) is implicitly used during subroutine
call, etc., a stack area must be specified for use by the user program.
There are no other internal I/O registers in which the initial value is changed.
FWE pins according to the mode setting conditions shown in Table 18.6.
At this time, this LSI latches the status of the mode pin inside the microcomputer to maintain
the boot mode status at the reset clear (startup with Low -> High) timing *
To clear boot mode, it is necessary to drive the FWE pin low during the reset, and then execute
reset release *
(a) Before making a transition from the boot mode to the regular mode, the microcomputer
(b) Do not change the input levels at the mode pins (MD
(c) Do not input low level to the FWE pin while the boot program is executing and when
during a reset (while a low level is being input to the RES pin), the microcomputer’s operating
mode will change.
Therefore, since the state of the address dual port and bus control output signals (AS, RD,
HWR, LWR) changes, use of these pins as output signals during reset must be disabled outside
the microcomputer.
boot mode must be reset by reset input via the RES pin. At this time, the RES pin must be
hold at low level for at least 20 system clock. *
boot mode. When making a mode transition, first enter the reset state by inputting a low
level to the RES pin. When a watchdog timer reset was generated in the boot mode, the
microcomputer mode is not reset and the on-chip boot program is restarted regardless of
the state of the mode pin.
programming/erasing flash memory. *
2. For notes on FWE pin High/Low, see section 18.9, Notes on Flash Memory
3. See section 4.2.2, Reset Sequence and 18.9, Notes on Flash Memory
relative to the reset clear timing.
Programming/Erasing.
Programming/Erasing. With the mask ROM version of the H8/3067, H8/3066, and
H8/3065, the minimum reset period during operation is 10 system clocks. However, the
1
. The following points must be noted:
2
1
DDR=1, P9DR P9
3
2
to MD
1
DR=1).
0
) or the FWE pin while in
CC
or from V
1
.
CC
to 0V
1
pin
MDS
)