HD64F3067RF20 Renesas Electronics America, HD64F3067RF20 Datasheet - Page 192

• Manufacturer Part Number: HD64F3067RF20
• Description: IC H8 MCU FLASH 128K 100-QFP
• Manufacturer: Renesas Electronics America
• Series: H8® H8/300Hr

Specifications of HD64F3067RF20

• Core Processor: H8/300H
• Core Size: 16-Bit
• Speed: 20MHz
• Connectivity: SCI, SmartCard
• Peripherals: DMA, PWM, WDT
• Number Of I /o: 70
• Program Memory Size: 128KB (128K x 8)
• Program Memory Type: FLASH
• Ram Size: 4K x 8
• Voltage - Supply (vcc/vdd): 4.5 V ~ 5.5 V
• Data Converters: A/D 8x10b; D/A 2x8b
• Oscillator Type: Internal
• Operating Temperature: -20°C ~ 75°C
• Package / Case: 100-QFP
• Package: 100PQFP
• Family Name: H8
• Maximum Speed: 20 MHz
• Operating Supply Voltage: 5 V
• Data Bus Width: 16|32 Bit
• Number Of Programmable I/os: 70
• Interface Type: SCI
• On-chip Adc: 8-chx10-bit
• On-chip Dac: 2-chx8-bit
• Number Of Timers: 7
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Eeprom Size: -

Section 6 Bus Controller
6.5.5
Table 6.7 shows the pins used for DRAM interfacing and their functions.
Table 6.7
Pin
PB4
PB5
HWR
LWR
CS
CS
CS
CS
RD
P80
A
D
Note: * Fixed high in a read access.
6.5.6
Figure 6.18 shows the basic access timing for DRAM space. The basic DRAM access timing is
four states: one precharge cycle (T
address output cycle (T
ASTCR control only enabling or disabling of wait insertion between T
the number of access states. When the corresponding bit in ASTCR is cleared to 0, wait states
cannot be inserted between T
Rev. 4.00 Jan 26, 2006 page 168 of 938
REJ09B0276-0400
12
15
2
3
4
5
to A
to D
0
0
Pins Used for DRAM Interface
With DRAM
Designated Name
UCAS
LCAS
UCAS
LCAS
RAS
RAS
RAS
RAS
WE
RFSH
A
D
Basic Timing
12
15
to A
to D
DRAM Interface Pins
2
3
4
5
0
0
c1
Upper column
address strobe
Lower column
address strobe
Upper column
address strobe
Lower column
address strobe
Row address
strobe 2
Row address
strobe 3
Row address
strobe 4
Row address
strobe 5
Write enable
Refresh
Address
Data
, T
c2
) states. Unlike the basic bus interface, the corresponding bits in
c1
and T
p
) state, one row address output cycle (T
c2
in the DRAM access cycle.
I/O
Output
Output
Output
Output
Output
Output
Output
Output
Output
Output
Output
I/O
Function
Upper column address strobe for DRAM
space access (when CSEL = 0 in DRCRB)
Lower column address strobe for DRAM
space access (when CSEL = 0 in DRCRB)
Upper column address strobe for DRAM
space access (when CSEL = 1 in DRCRB)
Lower column address strobe for DRAM
space access (when CSEL = 1 in DRCRB)
Row address strobe for DRAM space
access
Row address strobe for DRAM space
access
Row address strobe for DRAM space
access
Row address strobe for DRAM space
access
Write enable for DRAM space write
access*
Goes low in refresh cycle
Row address/column address multiplexed
output
Data input/output pins
c1
and T
r
) state, and two column
c2
, and do not affect