HD64F3067RF20 Renesas Electronics America, HD64F3067RF20 Datasheet - Page 255

• Manufacturer Part Number: HD64F3067RF20
• Description: IC H8 MCU FLASH 128K 100-QFP
• Manufacturer: Renesas Electronics America
• Series: H8® H8/300Hr

Specifications of HD64F3067RF20

• Core Processor: H8/300H
• Core Size: 16-Bit
• Speed: 20MHz
• Connectivity: SCI, SmartCard
• Peripherals: DMA, PWM, WDT
• Number Of I /o: 70
• Program Memory Size: 128KB (128K x 8)
• Program Memory Type: FLASH
• Ram Size: 4K x 8
• Voltage - Supply (vcc/vdd): 4.5 V ~ 5.5 V
• Data Converters: A/D 8x10b; D/A 2x8b
• Oscillator Type: Internal
• Operating Temperature: -20°C ~ 75°C
• Package / Case: 100-QFP
• Package: 100PQFP
• Family Name: H8
• Maximum Speed: 20 MHz
• Operating Supply Voltage: 5 V
• Data Bus Width: 16|32 Bit
• Number Of Programmable I/os: 70
• Interface Type: SCI
• On-chip Adc: 8-chx10-bit
• On-chip Dac: 2-chx8-bit
• Number Of Timers: 7
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Eeprom Size: -

7.4.2
I/O mode can be selected independently for each channel.
One byte or word is transferred at each transfer request in I/O mode. A designated number of these
transfers are executed. One address is specified in the memory address register (MAR), the other
in the I/O address register (IOAR). The direction of transfer is determined automatically from the
activation source. The transfer is from the address specified in IOAR to the address specified in
MAR if activated by an SCI channel 0 receive-data-full interrupt, and from the address specified
in MAR to the address specified in IOAR otherwise.
Table 7.6 indicates the register functions in I/O mode.
Table 7.6
Register
Legend
MAR:
IOAR: I/O address register
ETCR: Execute transfer count register
23
23
All 1s
Memory address register
15
I/O Mode
MAR
Register Functions in I/O Mode
ETCR
7
IOAR
0
0
0
Function
Activated by
SCI 0 Receive-
Data-Full
Interrupt or by
A/D Converter
Conversion-
End Interrupt
Destination
address
register
Source
address
register
Transfer counter
Other
Activation
Source
address
register
Destination
address
register
Rev. 4.00 Jan 26, 2006 page 231 of 938
Initial Setting
Destination or
source start
address
Source or
destination
address
Number of
transfers
Section 7 DMA Controller
REJ09B0276-0400
Operation
Incremented or
decremented
once per
transfer
Held fixed
Decremented
once per
transfer until
H'0000 is
reached and
transfer ends