HD64F3067RF20 Renesas Electronics America, HD64F3067RF20 Datasheet - Page 833

• Manufacturer Part Number: HD64F3067RF20
• Description: IC H8 MCU FLASH 128K 100-QFP
• Manufacturer: Renesas Electronics America
• Series: H8® H8/300Hr

Specifications of HD64F3067RF20

• Core Processor: H8/300H
• Core Size: 16-Bit
• Speed: 20MHz
• Connectivity: SCI, SmartCard
• Peripherals: DMA, PWM, WDT
• Number Of I /o: 70
• Program Memory Size: 128KB (128K x 8)
• Program Memory Type: FLASH
• Ram Size: 4K x 8
• Voltage - Supply (vcc/vdd): 4.5 V ~ 5.5 V
• Data Converters: A/D 8x10b; D/A 2x8b
• Oscillator Type: Internal
• Operating Temperature: -20°C ~ 75°C
• Package / Case: 100-QFP
• Package: 100PQFP
• Family Name: H8
• Maximum Speed: 20 MHz
• Operating Supply Voltage: 5 V
• Data Bus Width: 16|32 Bit
• Number Of Programmable I/os: 70
• Interface Type: SCI
• On-chip Adc: 8-chx10-bit
• On-chip Dac: 2-chx8-bit
• Number Of Timers: 7
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Eeprom Size: -

DRCRB—DRAM Control Register B
Initial value
Read/Write
Bit
Multiplex control 1 and 0
MXC1
MXC1
R/W
7
0
0
1
CAS output pin select
0
1
MXC0
MXC0
R/W
Refresh cycle enable
PB4 and PB5 selected as UCAS and LCAS output pins
HWR and LWR selected as UCAS and LCAS output pins
6
0
0
1
0
1
0
1
TP cycle control
0
1
Refresh cycles are disabled
DRAM refresh cycles are enabled
CSEL
Column address: 8 bits
Compared address:
Column address: 9 bits
Compared address:
Column address: 10 bits
Compared address:
Illegal setting
R/W
Modes 1, 2
Modes 3, 4, 5
Modes 1, 2
Modes 3, 4, 5
Modes 1, 2
Modes 3, 4, 5
5
0
1-state precharge cycle is inserted
2-state precharge cycle is inserted
RAS-CAS wait
0
1
Refresh cycle wait control
RCYCE
0
1
Wait state (T
1 wait state (T
R/W
4
0
Wait state (T
1 wait state (T
3
1
8-bit access space
16-bit access space
8-bit access space
16-bit access space
8-bit access space
16-bit access space
8-bit access space
16-bit access space
8-bit access space
16-bit access space
8-bit access space
16-bit access space
rw
) insertion is disabled
rw
Rev. 4.00 Jan 26, 2006 page 809 of 938
RW
) is inserted
Description
RW
TPC
R/W
) insertion is disabled
2
0
) is inserted
Appendix B Internal I/O Registers
RCW
H’EE027
R/W
1
0
RLW
R/W
0
0
A
A
A
A
A
A
A
A
A
A
A
A
19
19
23
23
19
19
23
23
19
19
23
23
to A
to A
to A
to A
to A
to A
to A
to A
to A
to A
to A
to A
8
9
8
9
9
10
9
10
10
11
10
11
REJ09B0276-0400
DRAM interface