HD64F3067RF20 Renesas Electronics America, HD64F3067RF20 Datasheet - Page 172

• Manufacturer Part Number: HD64F3067RF20
• Description: IC H8 MCU FLASH 128K 100-QFP
• Manufacturer: Renesas Electronics America
• Series: H8® H8/300Hr

Specifications of HD64F3067RF20

• Core Processor: H8/300H
• Core Size: 16-Bit
• Speed: 20MHz
• Connectivity: SCI, SmartCard
• Peripherals: DMA, PWM, WDT
• Number Of I /o: 70
• Program Memory Size: 128KB (128K x 8)
• Program Memory Type: FLASH
• Ram Size: 4K x 8
• Voltage - Supply (vcc/vdd): 4.5 V ~ 5.5 V
• Data Converters: A/D 8x10b; D/A 2x8b
• Oscillator Type: Internal
• Operating Temperature: -20°C ~ 75°C
• Package / Case: 100-QFP
• Package: 100PQFP
• Family Name: H8
• Maximum Speed: 20 MHz
• Operating Supply Voltage: 5 V
• Data Bus Width: 16|32 Bit
• Number Of Programmable I/os: 70
• Interface Type: SCI
• On-chip Adc: 8-chx10-bit
• On-chip Dac: 2-chx8-bit
• Number Of Timers: 7
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Eeprom Size: -

Section 6 Bus Controller
Table 6.3
ABWCR ASTCR WCRH/WCRL
ABWn
0
1
Note: n = 7 to 0
6.3.3
The H8/3067 Group memory interfaces comprise a basic bus interface that allows direct
connection of ROM, SRAM, and so on; a DRAM interface that allows direct connection of
DRAM; and a burst ROM interface that allows direct connection of burst ROM. The interface can
be selected independently for each area.
An area for which the basic bus interface is designated functions as normal space, an area for
which the DRAM interface is designated functions as DRAM space, and area 0 for which the burst
ROM interface is designated functions as burst ROM space.
6.3.4
For each of areas 0 to 7, the H8/3067 Group can output a chip select signal (CS
low when the corresponding area is selected in expanded mode. Figure 6.4 shows the output
timing of a CSn signal.
Output of CS
(DDR) of the corresponding port.
In the expanded modes with on-chip ROM disabled, a reset leaves pin CS
pins CS
bits must be set to 1. In the expanded modes with on-chip ROM enabled, a reset leaves pins CS
Rev. 4.00 Jan 26, 2006 page 148 of 938
REJ09B0276-0400
1
to CS
ASTn
0
1
0
1
Memory Interfaces
Chip Select Signals
CS
CS
CS
Bus Specifications for Each Area (Basic Bus Interface)
0
3
to CS
in the input state. To output chip select signals CS
CS
CS
CS
Wn1
—
0
1
—
0
1
3
: Output of CS
Wn0
—
0
1
0
1
—
0
1
0
1
0
to CS
Bus Width
16
8
Bus Specifications (Basic Bus Interface)
3
is enabled or disabled in the data direction register
Access States
2
3
2
3
1
to CS
3
, the corresponding DDR
0
in the output state and
Program Wait States
0
0
1
2
3
0
0
1
2
3
0
to CS
7
) that goes
0
to