HD64F3067RF20 Renesas Electronics America, HD64F3067RF20 Datasheet - Page 869

• Manufacturer Part Number: HD64F3067RF20
• Description: IC H8 MCU FLASH 128K 100-QFP
• Manufacturer: Renesas Electronics America
• Series: H8® H8/300Hr

Specifications of HD64F3067RF20

• Core Processor: H8/300H
• Core Size: 16-Bit
• Speed: 20MHz
• Connectivity: SCI, SmartCard
• Peripherals: DMA, PWM, WDT
• Number Of I /o: 70
• Program Memory Size: 128KB (128K x 8)
• Program Memory Type: FLASH
• Ram Size: 4K x 8
• Voltage - Supply (vcc/vdd): 4.5 V ~ 5.5 V
• Data Converters: A/D 8x10b; D/A 2x8b
• Oscillator Type: Internal
• Operating Temperature: -20°C ~ 75°C
• Package / Case: 100-QFP
• Package: 100PQFP
• Family Name: H8
• Maximum Speed: 20 MHz
• Operating Supply Voltage: 5 V
• Data Bus Width: 16|32 Bit
• Number Of Programmable I/os: 70
• Interface Type: SCI
• On-chip Adc: 8-chx10-bit
• On-chip Dac: 2-chx8-bit
• Number Of Timers: 7
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Eeprom Size: -

TCR0—Timer Control Register 0
TCR1—Timer Control Register 1
Initial value
Read/Write
Bit
CMIEB
Compare match interrupt enable B
R/W
0
1
7
0
CMIB interrupt requested by CMFB is disabled
CMIB interrupt requested by CMFB is enabled
CMIEA
Compare match interrupt enable A
R/W
0
1
6
0
CMIA interrupt requested by CMFA is disabled
CMIA interrupt requested by CMFA is enabled
Timer overflow interrupt enable
OVIE
R/W
0
1
5
0
OVI interrupt requested by OVF is disabled
OVI interrupt requested by OVF is enabled
Counter clear 1 and 0
CCLR1
0
1
R/W
4
0
0
1
0
1
CCLR0
Notes: * If the clock input of channel 0 is the TCNT1
R/W
Clock select 2 to 0
Clearing is disabled
Cleared by compare match A
Cleared by compare match B/input capture B
Cleared by input capture B
3
0
0
1
H’FFF80
H’FFF81
0
1
0
1
overflow signal and that of channel 1 is the
TCNT0 compare match signal, no
incrementing clock is generated. Do not use
this setting.
CKS2
Rev. 4.00 Jan 26, 2006 page 845 of 938
R/W
2
0
0
1
0
1
0
1
0
1
Internal clock, counted on rising
edge of /8
Internal clock, counted on rising
edge of /64
Internal clock, counted on rising
edge of /8192
Channel 0:
Channel 1:
External clock, counted on falling edge
External clock, counted on rising edge
External clock, counted on both
rising and falling edges
Clock input is disabled
Appendix B Internal I/O Registers
Count on TCNT1 overflow signal*
Count on TCNT0 compare match
A*
CKS1
R/W
1
0
CKS0
R/W
8-bit timer channel 0
8-bit timer channel 1
0
0
REJ09B0276-0400