HD64F3067RF20 Renesas Electronics America, HD64F3067RF20 Datasheet - Page 71

IC H8 MCU FLASH 128K 100-QFP

HD64F3067RF20

Manufacturer Part Number
HD64F3067RF20
Description
IC H8 MCU FLASH 128K 100-QFP
Manufacturer
Renesas Electronics America
Series
H8® H8/300Hr
Datasheet

Specifications of HD64F3067RF20

Core Processor
H8/300H
Core Size
16-Bit
Speed
20MHz
Connectivity
SCI, SmartCard
Peripherals
DMA, PWM, WDT
Number Of I /o
70
Program Memory Size
128KB (128K x 8)
Program Memory Type
FLASH
Ram Size
4K x 8
Voltage - Supply (vcc/vdd)
4.5 V ~ 5.5 V
Data Converters
A/D 8x10b; D/A 2x8b
Oscillator Type
Internal
Operating Temperature
-20°C ~ 75°C
Package / Case
100-QFP
Package
100PQFP
Family Name
H8
Maximum Speed
20 MHz
Operating Supply Voltage
5 V
Data Bus Width
16|32 Bit
Number Of Programmable I/os
70
Interface Type
SCI
On-chip Adc
8-chx10-bit
On-chip Dac
2-chx8-bit
Number Of Timers
7
Lead Free Status / RoHS Status
Contains lead / RoHS non-compliant
Eeprom Size
-

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Before Execution of BCLR Instruction
Execution of BCLR Instruction
BCLR #0, @P4DDR ;Clear bit 0 in data direction register
After Execution of BCLR Instruction
Explanation: To execute the BCLR instruction, the CPU begins by reading P4DDR. Since
P4DDR is a write-only register, it is read as H'FF, even though its true value is H'3F.
Next the CPU clears bit 0 of the read data, changing the value to H'FE.
Finally, the CPU writes this value (H'FE) back to P4DDR to complete the BCLR instruction.
As a result, P4
are set to 1, making P4
The BCLR instruction can be used to clear flags in the on-chip registers to 0. In an interrupt-
handling routine, for example, if it is known that the flag is set to 1, it is not necessary to read the
flag ahead of time.
Input/output
DDR
Input/output
DDR
0
DDR is cleared to 0, making P4
P4
Input
0
P4
Output
1
7
7
7
and P4
P4
Input
0
P4
1
Output
6
6
6
output pins.
P4
Output
1
P4
Output
1
5
5
P4
Output
1
P4
Output
1
0
an input pin. In addition, P4
4
4
P4
Output
1
P4
Output
1
Rev. 4.00 Jan 26, 2006 page 47 of 938
3
3
P4
Output
1
P4
Output
1
2
2
7
P4
Output
1
P4
Output
1
DDR and P4
REJ09B0276-0400
1
1
Section 2 CPU
P4
Output
1
P4
Input
0
6
0
0
DDR

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