HD64F3067RF20 Renesas Electronics America, HD64F3067RF20 Datasheet - Page 372

IC H8 MCU FLASH 128K 100-QFP

HD64F3067RF20

Manufacturer Part Number
HD64F3067RF20
Description
IC H8 MCU FLASH 128K 100-QFP
Manufacturer
Renesas Electronics America
Series
H8® H8/300Hr
Datasheet

Specifications of HD64F3067RF20

Core Processor
H8/300H
Core Size
16-Bit
Speed
20MHz
Connectivity
SCI, SmartCard
Peripherals
DMA, PWM, WDT
Number Of I /o
70
Program Memory Size
128KB (128K x 8)
Program Memory Type
FLASH
Ram Size
4K x 8
Voltage - Supply (vcc/vdd)
4.5 V ~ 5.5 V
Data Converters
A/D 8x10b; D/A 2x8b
Oscillator Type
Internal
Operating Temperature
-20°C ~ 75°C
Package / Case
100-QFP
Package
100PQFP
Family Name
H8
Maximum Speed
20 MHz
Operating Supply Voltage
5 V
Data Bus Width
16|32 Bit
Number Of Programmable I/os
70
Interface Type
SCI
On-chip Adc
8-chx10-bit
On-chip Dac
2-chx8-bit
Number Of Timers
7
Lead Free Status / RoHS Status
Contains lead / RoHS non-compliant
Eeprom Size
-

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Section 9 16-Bit Timer
9.2.6
TISRC is an 8-bit readable/writable register that indicates TCNT overflow or underflow and
enables or disables overflow interrupt requests.
TISRC is initialized to H'88 by a reset and in standby mode.
Bit 7—Reserved: This bit cannot be modified and is always read as 1.
Bit 6—Overflow Interrupt Enable 2 (OVIE2): Enables or disables the interrupt requested by the
OVF2 flag when OVF2 is set to 1.
Bit 6
OVIE2
0
1
Rev. 4.00 Jan 26, 2006 page 348 of 938
REJ09B0276-0400
Initial value
Read/Write
Note: * Only 0 can be written, to clear the flag.
Timer Interrupt Status Register C (TISRC)
OVI2 interrupt requested by OVF2 flag is disabled
Description
Bit
OVI2 interrupt requested by OVF2 flag is enabled
Reserved bit
7
1
OVIE2
R/W
6
0
Overflow interrupt enable 2 to 0
These bits enable or disable interrupts by the OVF flags
OVIE1
R/W
5
0
OVIE0
R/W
4
0
Reserved bit
3
1
R/(W)*
OVF2
Overflow flags 2 to 0
Status flags indicating overflow
or underflow
2
0
R/(W)*
OVF1
1
0
R/(W)*
OVF0
0
0
(Initial value)

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