HD64F3067RF20 Renesas Electronics America, HD64F3067RF20 Datasheet - Page 16

• Manufacturer Part Number: HD64F3067RF20
• Description: IC H8 MCU FLASH 128K 100-QFP
• Manufacturer: Renesas Electronics America
• Series: H8® H8/300Hr

Specifications of HD64F3067RF20

• Core Processor: H8/300H
• Core Size: 16-Bit
• Speed: 20MHz
• Connectivity: SCI, SmartCard
• Peripherals: DMA, PWM, WDT
• Number Of I /o: 70
• Program Memory Size: 128KB (128K x 8)
• Program Memory Type: FLASH
• Ram Size: 4K x 8
• Voltage - Supply (vcc/vdd): 4.5 V ~ 5.5 V
• Data Converters: A/D 8x10b; D/A 2x8b
• Oscillator Type: Internal
• Operating Temperature: -20°C ~ 75°C
• Package / Case: 100-QFP
• Package: 100PQFP
• Family Name: H8
• Maximum Speed: 20 MHz
• Operating Supply Voltage: 5 V
• Data Bus Width: 16|32 Bit
• Number Of Programmable I/os: 70
• Interface Type: SCI
• On-chip Adc: 8-chx10-bit
• On-chip Dac: 2-chx8-bit
• Number Of Timers: 7
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Eeprom Size: -

10.2 Register Descriptions ........................................................................................................ 402
10.3 CPU Interface.................................................................................................................... 413
10.4 Operation .......................................................................................................................... 415
10.5 Interrupts ........................................................................................................................... 423
10.6 8-Bit Timer Application Example..................................................................................... 424
10.7 Usage Notes ...................................................................................................................... 425
Section 11 Programmable Timing Pattern Controller (TPC)
11.1 Overview........................................................................................................................... 435
Rev. 4.00 Jan 26, 2006 page xiv of xxii
10.1.2 Block Diagram ..................................................................................................... 399
10.1.3 Pin Configuration................................................................................................. 400
10.1.4 Register Configuration......................................................................................... 401
10.2.1 Timer Counters (TCNT) ...................................................................................... 402
10.2.2 Time Constant Registers A (TCORA) ................................................................. 403
10.2.3 Time Constant Registers B (TCORB).................................................................. 404
10.2.4 Timer Control Register (TCR) ............................................................................. 405
10.2.5 Timer Control/Status Registers (TCSR) .............................................................. 408
10.3.1 8-Bit Registers ..................................................................................................... 413
10.4.1 TCNT Count Timing............................................................................................ 415
10.4.2 Compare Match Timing....................................................................................... 416
10.4.3 Input Capture Signal Timing ............................................................................... 417
10.4.4 Timing of Status Flag Setting .............................................................................. 418
10.4.5 Operation with Cascaded Connection.................................................................. 419
10.4.6 Input Capture Setting ........................................................................................... 421
10.5.1 Interrupt Sources.................................................................................................. 423
10.5.2 A/D Converter Activation.................................................................................... 424
10.7.1 Contention between TCNT Write and Clear........................................................ 425
10.7.2 Contention between TCNT Write and Increment ................................................ 426
10.7.3 Contention between TCOR Write and Compare Match ...................................... 427
10.7.4 Contention between TCOR Read and Input Capture ........................................... 428
10.7.5 Contention between Counter Clearing by Input Capture
10.7.6 Contention between TCOR Write and Input Capture .......................................... 430
10.7.7 Contention between TCNT Byte Write and Increment in 16-Bit Count Mode
10.7.8 Contention between Compare Matches A and B ................................................. 432
10.7.9 TCNT Operation at Internal Clock Source Switchover ....................................... 432
11.1.1 Features................................................................................................................ 435
11.1.2 Block Diagram ..................................................................................................... 436
11.1.3 TPC Pins .............................................................................................................. 437
11.1.4 Registers............................................................................................................... 438
and Counter Increment......................................................................................... 429
(Cascaded Connection) ........................................................................................ 431
.................................. 435