MC908AZ60ACFU Freescale Semiconductor, MC908AZ60ACFU Datasheet - Page 351

• Manufacturer Part Number: MC908AZ60ACFU
• Description: IC MCU FLASH 8.4MHZ 60K 64QFP
• Manufacturer: Freescale Semiconductor
• Series: HC08r

Specifications of MC908AZ60ACFU

• Core Processor: HC08
• Core Size: 8-Bit
• Speed: 8.4MHz
• Connectivity: CAN, SCI, SPI
• Peripherals: LVD, POR, PWM
• Number Of I /o: 52
• Program Memory Size: 60KB (60K x 8)
• Program Memory Type: FLASH
• Eeprom Size: 1K x 8
• Ram Size: 2K x 8
• Voltage - Supply (vcc/vdd): 4.5 V ~ 5.5 V
• Data Converters: A/D 15x8b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 64-QFP
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant

Once the Tx shift register has completed its shifting operation for the current byte, the data byte in the Tx
shadow register is loaded into the Tx shift register. After this transfer takes place, the Tx shadow register
is ready to accept new data from the CPU when TDRE flag in BSVR is set.
27.5.4 Digital Loopback Multiplexer
The digital loopback multiplexer connects RxD to either BDTxD or BDRxD, depending on the state of the
DLOOP bit in the BCR2 register (see
27.5.5 State Machine
All of the functions associated with performing the protocol are executed or controlled by the state
machine. The state machine is responsible for framing, collision detection, arbitration, CRC
generation/checking, and error detection. The following sections describe the BDLC’s actions in a variety
of situations.
27.5.5.1 4X Mode
The BDLC can exist on the same J1850 bus as modules which use a special 4X (41.6 kbps) mode of
J1850 variable pulse width modulation (VPW) operation. The BDLC cannot transmit in 4X mode, but can
receive messages in 4X mode, if the RX4X bit is set in BCR2 register. If the RX4X bit is not set in the
BCR2 register, any 4X message on the J1850 bus is treated as noise by the BDLC and is ignored.
27.5.5.2 Receiving a Message in Block Mode
Although not a part of the SAE J1850 protocol, the BDLC does allow for a special block mode of operation
of the receiver. As far as the BDLC is concerned, a block mode message is simply a long J1850 frame
that contains an indefinite number of data bytes. All of the other features of the frame remain the same,
including the SOF, CRC, and EOD symbols.
Another node wishing to send a block mode transmission must first inform all other nodes on the network
that this is about to happen. This is usually accomplished by sending a special predefined message.
27.5.5.3 Transmitting a Message in Block Mode
A block mode message is transmitted inherently by simply loading the bytes one by one into the BDR
register until the message is complete. The programmer should wait until the TDRE flag (see
State Vector
contain any predefined maximum J1850 message length requirement.
27.5.5.4 J1850 Bus Errors
The BDLC detects several types of transmit and receive errors which can occur during the transmission
of a message onto the J1850 bus.
Transmission Error
Freescale Semiconductor
If the message transmitted by the BDLC contains invalid bits or framing symbols on non-byte
boundaries, this constitutes a transmission error. When a transmission error is detected, the BDLC
immediately will cease transmitting. The error condition ($1C) is reflected in the BSVR register (see
Table
generated.
27-5). If the interrupt enable bit (IE in BCR1) is set, a CPU interrupt request from the BDLC is
Register) is set prior to writing a new byte of data into the BDR register. The BDLC does not
MC68HC908AZ60A • MC68HC908AS60A • MC68HC908AS60E Data Sheet, Rev. 6
27.6.3 BDLC Control Register
2).
BDLC Protocol Handler
27.6.4 BDLC
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