WG82574L S LBA9 Intel, WG82574L S LBA9 Datasheet - Page 157

• Manufacturer Part Number: WG82574L S LBA9
• Description: CONTROLLER, ENET, INTEL 82574L, 64PQFN
• Manufacturer: Intel

Specifications of WG82574L S LBA9

• Ethernet Type: IEEE 802.3, IEEE 802.3u, IEEE 802.3ab
• Supply Voltage Range: 3V To 3.6V
• Operating Temperature Range: 0°C To +85°C
• Digital Ic Case Style: QFN
• No. Of Pins: 64
• Package / Case: QFN
• Interface Type: I2C, JTAG, PCI, SPI
• Rohs Compliant: Yes
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

Inline Functions—82574 GbE Controller
7.2.4
Figure 34.
Transmit Descriptor Ring Structure
The transmit descriptor ring is described by the following registers:
Transmit Descriptor Ring Structure
• Software places the rest of the data to be transmitted in the host memory indicated
• Hardware splits the data into multiple packets according to the Maximum Segment
• For each packet, the proceeding steps are the same as the legacy Tx descriptors as
• Transmit Descriptor Base Address register (TDBA)
• Transmit Descriptor Length register (TDLEN)
• Transmit Descriptor Head register (TDH)
• Transmit Descriptor Tail register (TDT)
to the hardware by additional data descriptors.
Size (MSS) defined in the context descriptor. Hardware uses the prototype header
for each packet while it auto-updates some of the fields in the IP and TCP headers.
See more details in
previously described (starting at step number 4).
— This register indicates the start address of the descriptor ring buffer in the host
— This register determines the number of bytes allocated to the circular ring. This
— This register holds an index value that indicates the in-progress descriptor.
— This register holds a value, which is an offset from the base (TDBA), and
memory; this 64-bit address is aligned on a 16-byte boundary and is stored in
two consecutive 32-bit registers. Hardware ignores the lower four bits.
value must be aligned to 128 bytes.
There can be up to 64 KB descriptors in the circular buffer. Reading this register
returns the value of head corresponding to descriptors already loaded in the
transmit FIFO.
indicates the location beyond the last descriptor hardware can process. This is
the location where software writes the next new descriptor.
section
7.3.6.2.
TDLEN
Base +
TDBA
Base
Base+1
TDT
Tail
Head
TDH
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