WG82574L S LBA9 Intel, WG82574L S LBA9 Datasheet - Page 294

• Manufacturer Part Number: WG82574L S LBA9
• Description: CONTROLLER, ENET, INTEL 82574L, 64PQFN
• Manufacturer: Intel

Specifications of WG82574L S LBA9

• Ethernet Type: IEEE 802.3, IEEE 802.3u, IEEE 802.3ab
• Supply Voltage Range: 3V To 3.6V
• Operating Temperature Range: 0°C To +85°C
• Digital Ic Case Style: QFN
• No. Of Pins: 64
• Package / Case: QFN
• Interface Type: I2C, JTAG, PCI, SPI
• Rohs Compliant: Yes
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

294
SPEED
Reserved
FRCSPD
FRCDPLX
Reserved
ADVD3WUC
Reserved
RST
RFCE
TFCE
Reserved
VME
Field
9:8
10
11
12
19:13
20
25:21
26
27
28
29
30
Bit(s)
10b
0b
0b
0b
0x0
1b
0x0
0b
0b
0b
0b
0b
Initial
Value
1
Speed selection
These bits can determine the speed configuration and are written by
software after reading the PHY configuration through the MDIO
interface. These signals are ignored when Auto-Speed Detection is
enabled.
00b = 10 Mb/s
01b = 100 Mb/s
10b = 1000 Mb/s
11b =not used
Reserved
Write as 0b for future compatibility.
Force Speed
This bit is set when software wants to manually configure the MAC
speed settings according to the Speed bits. When using a PHY device,
note that the PHY device must resolve to the same speed
configuration, or software must manually set it to the same speed as
the MAC. Note that this bit is superseded by the CTRL_EXT.SPD_BYPS
bit which has a similar function.
Force Duplex
When set to 1b, software might override the duplex indication from
the PHY that is indicated in the FDX to the MAC. Otherwise, the
duplex setting is sampled from the PHY FDX indication into the MAC
on the asserting edge of the PHY LINK signal. When asserted, the
CTRL.FD bit sets duplex.
Reserved
Reads as 0b.
D3Cold WakeUp Capability Advertisement Enable
When set, D3Cold wakeup capability is advertised based on whether
the AUX_PWR advertises presence of auxiliary power (yes if
AUX_PWR is indicated, no otherwise). When 0b, however, D3Cold
wakeup capability is not advertised even if AUX_PWR presence is
indicated.
Note: This bit must be set to 1b.
Reserved
Device Reset
This bit performs a reset of the MAC function of the device, as
described in
reset. This bit is self-clearing.
Receive Flow Control Enable
Indicates that the device responds to the reception of flow control
packets. Reception of flow control packets requires the correct loading
of the FCAL/H and FCT registers. If auto-negotiation is enabled, this
bit is set to the negotiated duplex value. See
information about auto-negotiation.
Transmit Flow Control Enable
Indicates that the device transmits flow control packets (XON and
XOFF frames) based on receiver fullness. If auto-negotiation is
enabled, this bit is set to the negotiated duplex value. See
Section 3.2.3
Reserved
Reads as 0b.
VLAN Mode Enable
When set to 1b, all packets transmitted from the 82574 that have VLE
set is sent with an 802.1Q header added to the packet. The contents
of the header come from the transmit descriptor and from the VLAN
type register. On receive, VLAN information is stripped from 802.1Q
packets. See
See
82574 GbE Controller—Driver Programing Interface
Section
Section 7.5.1
for more information about auto-negotiation.
Section 3.2.1
10.2.2.2. Normally 0b; writing 1b initiates the
for more details.
Description
for details.
Section 3.2.3
for more