WG82574L S LBA9 Intel, WG82574L S LBA9 Datasheet - Page 302

• Manufacturer Part Number: WG82574L S LBA9
• Description: CONTROLLER, ENET, INTEL 82574L, 64PQFN
• Manufacturer: Intel

Specifications of WG82574L S LBA9

• Ethernet Type: IEEE 802.3, IEEE 802.3u, IEEE 802.3ab
• Supply Voltage Range: 3V To 3.6V
• Operating Temperature Range: 0°C To +85°C
• Digital Ic Case Style: QFN
• No. Of Pins: 64
• Package / Case: QFN
• Interface Type: I2C, JTAG, PCI, SPI
• Rohs Compliant: Yes
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

Note:
Note:
10.2.2.7
302
This register provides the software with direct access to the Flash. Software can control
the Flash by successive writes to this register. Data and address information is clocked
into the Flash by software toggling the FL_NVM_SK bit (0) of this register with FL_CE
set to 1. Data output from the Flash is latched into bit 3 of this register via the internal
125 MHz clock and may be accessed by software via reads of this register.
In the 82574, the FLA register is only reset at Internal Power On Reset and not as
legacy devices at a software reset.
MDI Control Register - MDIC (0x00020; RW)
This register is used by software to read or write Management Data Interface (MDI)
registers in a GMII/MII PHY.
Reserved
Reserved
FL_BUSY
FL_ER
DATA
REGADD
PHYADD
OP
R
I
E
Reserved
Field
Field
15:0
20:16
25:21
27:26
28
29
30
31
Bit(s)
10
29:11
30
31
Bit(s)
X
0x0
0x0
0x0
1b
0b
0b
0b
Initial
Value
1b
0x0
0b
0b
Initial
Value
Data
In a Write command, software places the data bits and the MAC shifts
them out to the PHY. In a Read command, the MAC reads these bits
serially from the PHY and software can read them from this location.
PHY register address; i.e., Reg 0, 1, 2, … 31.
PHY Address
1 = Gigabit PHY.
2 = PCIe PHY.
Op-Code
01b = MDI write.
10b = MDI read.
Other values are reserved.
Ready Bit
Set to 1b by the 82574 at the end of the MDI transaction (for
example, indicates a read or write has been completed). It should be
reset to 0b by software at the same time the command is written.
Interrupt Enable
When set to 1b by software, it causes an Interrupt to be asserted to
indicate the end of an MDI cycle.
Error
This bit set is to 1b by hardware when it fails to complete an MDI
read. Software should make sure this bit is clear (0b) before making
an MDI Read or Write command.
Reserved. Write as 0b for future compatibility.
Reserved
Reserved
Reads as 0b.
Flash Busy
This bit is set to 1b while a transaction to the Flash is in progress.
While this bit is clear (read as 0b), software can access the Flash.
This field is read only.
Flash Erase Command
The command is sent to the Flash only if bits 5:4 in the EEC
register are set to 00b. This bit is auto-cleared and read as 0b.
Certain Flash vendors do not support this operation.
82574 GbE Controller—Driver Programing Interface
Description
Description