WG82574L S LBA9 Intel, WG82574L S LBA9 Datasheet - Page 160

• Manufacturer Part Number: WG82574L S LBA9
• Description: CONTROLLER, ENET, INTEL 82574L, 64PQFN
• Manufacturer: Intel

Specifications of WG82574L S LBA9

• Ethernet Type: IEEE 802.3, IEEE 802.3u, IEEE 802.3ab
• Supply Voltage Range: 3V To 3.6V
• Operating Temperature Range: 0°C To +85°C
• Digital Ic Case Style: QFN
• No. Of Pins: 64
• Package / Case: QFN
• Interface Type: I2C, JTAG, PCI, SPI
• Rohs Compliant: Yes
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

Note:
Note:
7.2.7
Note:
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The device automatically selects the appropriate mode to use based on the current
packet transmission: legacy, extended, or segmentation.
While the architecture supports arbitrary ordering rules for the various descriptors,
there are restrictions including:
There are dedicated resources on-chip for both the extended and segmentation modes.
These modes remain constant until they are modified by another context descriptor.
This means that a set of configurations relevant to one mode can (and will) be used for
multiple packets unless a new mode is loaded prior to sending a new packet.
When working with two descriptor queues in the 82574, the software needs to rewrite
the context descriptor for each packet as it can't know if the second queue transmission
had modified the on-chip context or not. The hardware keeps track of only the last
context descriptor that was written.
Pipelined Tx Data Read Requests
Transmit data request pipelining is the process by which a request for transmit data is
sent to the host memory before the read DMA request of the previously requested data
completes. Transmit pipeline requests is enabled using the MULR bit in the Transmit
Control (TCTL) register, Its initial value is loaded from the NVM.
The 82574L supports four pipelined requests from the Tx data DMA. In general, the
four requests can belong to the same packet or to consecutive packets. However, the
following restrictions apply:
The PCIe specification does not ensure that completions for separate requests return in
order. The 82574L can handle completions that arrive in any order.
The 82574L incorporates a 2 KB buffer to support re-ordering of completions for the
four requests. Each request/completion can be up to 512 bytes long. The maximum
size of a read request is defined as follows:
In addition to the four pipeline requests from the Tx data DMA, the 82574 can issue a
single read request from each of the 2 Tx descriptor and 2 Rx descriptor DMA engines.
The requests from the three sources (Tx data, Tx descriptor and Rx descriptor) are
independently issued. Each descriptor read request can fetch up to 16 descriptors
(equal to 256 bytes of data).
• All requests for a packet are issued before a request is issued for a following
• If a request (for the following packet) requires context change, the request for the
• When the MULR bit is cleared, maximum request size in bytes is the min{2K,
• When the MULR bit is set, maximum request size in bytes is the min{512,
packet.
following packet is not issued until the previous request is completed (such as, no
pipeline across contexts).
Max_Read_Request_Size}
Max_Read_Request_Size}
— Context descriptors should not occur in the middle of a packet or of a
— Data descriptors of different packet types (legacy, extended, or segmentation)
segmentation.
should not be intermingled except at the packet (or segmentation) level.
82574 GbE Controller—Inline Functions