WG82574L S LBA9 Intel, WG82574L S LBA9 Datasheet - Page 461

• Manufacturer Part Number: WG82574L S LBA9
• Description: CONTROLLER, ENET, INTEL 82574L, 64PQFN
• Manufacturer: Intel

Specifications of WG82574L S LBA9

• Ethernet Type: IEEE 802.3, IEEE 802.3u, IEEE 802.3ab
• Supply Voltage Range: 3V To 3.6V
• Operating Temperature Range: 0°C To +85°C
• Digital Ic Case Style: QFN
• No. Of Pins: 64
• Package / Case: QFN
• Interface Type: I2C, JTAG, PCI, SPI
• Rohs Compliant: Yes
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

Design Considerations—82574 GbE Controller
Note:
13.8.1
13.9
13.9.1
Warning:
The DEV_OFF_N pin should maintain its state during system reset and system sleep
states. It should also insure the proper default value on system power up. For example,
a designer could use a GPIO pin that defaults to 1b (enable) and is on system suspend
power. For example, it maintains the state in S0-S5 ACPI states).
BIOS Handling of Device Disable
Assume that in the following power-up sequence the DEV_OFF_N signal is driven high
(or it is already disabled)
82574L Exposed Pad*
Introduction
The 82574L is a 64-pin, 9 x 9 QFN package with an Exposed-Pad*. The Exposed-Pad*
is a central pad on the bottom of the package that provides the primary heat removal
path as well as electrical grounding for a Printed Circuit Board (PCB).
In order to maximize both the removal of heat from the package and the electrical
performance, a landing pattern must be incorporated on the PCB within the footprint of
the package corresponding to the exposed metal pad or exposed heat slug on the
package. The size of the landing pattern can be larger, smaller, or even take on a
different shape than the Exposed-Pad* on the package. However, the solderable area,
as defined by the solder mask, should be at least the same size/shape as the Exposed-
Pad* on the package to maximize the thermal/electrical performance.
While the landing pattern on the PCB provides a means of heat transfer/electrical
grounding from the package to the board through a solder joint, thermal vias are
necessary to effectively conduct from the surface of the PCB to the ground plane(s).
The number of vias are application specific and dependent upon the package power
dissipation as well as electrical conductivity requirements. As a result, thermal and
electrical analysis and/or testing are recommended to determine the minimum number
needed.
Make sure that the 82574 has a good connection to ground. Check for solder voids on
the Exposed Pad,* solder wicking, or a complete lack of solder. Failure to ensure a good
connection to ground can result in functional failure.
The remainder of this section describes the silkscreen/component pads, solder mask,
solder paste, and two potential landing patterns that can be used for the 82574
package. Note that these potential landing patterns have been used successfully in past
designs, however no particular landing pattern is recommended. Please work with your
manufacturer and assembler to ensure a process that is reliable.
1. The PCIe is established following the GIO_PWR_GOOD.
2. BIOS recognizes that the entire 82574L should be disabled.
3. The BIOS drives the DEV_OFF_N signal to the low level.
4. As a result, the 82574 samples the DEV_OFF_N signals and enters either the device
5. The BIOS could put the link in the Electrical IDLE state (at the other end of the PCIe
6. BIOS might start with the device enumeration procedure (the entire 82574L
7. Proceed with normal operation
8. Re-enable could be done by driving high the DEV_OFF_N signal, followed later by
disable mode.
link) by clearing the Link Disable bit in the Link Control register.
functions are invisible).
bus enumeration.
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