WG82574L S LBA9 Intel, WG82574L S LBA9 Datasheet - Page 460

• Manufacturer Part Number: WG82574L S LBA9
• Description: CONTROLLER, ENET, INTEL 82574L, 64PQFN
• Manufacturer: Intel

Specifications of WG82574L S LBA9

• Ethernet Type: IEEE 802.3, IEEE 802.3u, IEEE 802.3ab
• Supply Voltage Range: 3V To 3.6V
• Operating Temperature Range: 0°C To +85°C
• Digital Ic Case Style: QFN
• No. Of Pins: 64
• Package / Case: QFN
• Interface Type: I2C, JTAG, PCI, SPI
• Rohs Compliant: Yes
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

13.7.2
13.8
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Power and Ground Planes
Good grounding requires minimizing inductance levels in the interconnections and
keeping ground returns short, signal loop areas small, and power inputs bypassed to
signal return, will significantly reduce EMI radiation.
The following guidelines help reduce circuit inductance in both backplanes and
motherboards:
Device Disable
For a LOM design, it might be desirable for the system to provide BIOS-setup capability
for selectively enabling or disabling LOM devices. This enables designers more control
over system resource-management, avoid conflicts with add-in NIC solutions, etc. The
82574L provides support for selectively enabling or disabling it.
Device disable is initiated by asserting the asynchronous DEV_OFF_N pin. The
DEV_OFF_N pin has an internal pull-up resistor, so that it can be left not connected to
enable device operation.
While in device disable mode, the PCIe link is in L3 state. The PHY is in power down
mode. Output buffers are tri-stated.
Assertion or deassertion of PCIe PE_RST_N does not have any effect while the 82574 is
in device disable mode (that is, the 82574 stays in the respective mode as long as
DEV_OFF_N is asserted). However, the 82574 might momentarily exit the device
disable mode from the time PCIe PE_RST_N is de-asserted again and until the NVM is
read.
During power-up, the DEV_OFF_N pin is ignored until the NVM is read. From that point,
the 82574 might enter device disable if DEV_OFF_N is asserted.
• Route traces over a continuous plane with no interruptions. Do not route over a
• Separate noisy digital grounds from analog grounds to reduce coupling. Noisy
• All ground vias should be connected to every ground plane; and every power via
• Physically locate grounds between a signal path and its return. This will minimize
• Avoid fast rise/fall times as much as possible. Signals with fast rise and fall times
• The ground plane beneath a magnetics module should be split. The RJ45 connector
• Power delivery traces should be a minimum of 100 mils wide at all places from the
split power or ground plane. If there are vacant areas on a ground or power plane,
avoid routing signals over the vacant area. This will increase inductance and EMI
radiation levels.
digital grounds may affect sensitive DC subsystems.
should be connected to all power planes at equal potential. This helps reduce circuit
inductance.
the loop area.
contain many high frequency harmonics, which can radiate EMI.
side of the transformer module should have chassis ground beneath it.
source to the destination. As power flows through pass transistors or regulators,
the traces must be kept wide as well. The distribution of power is better done with
a copper-pore under the PHY. This provides low inductance connectivity to
decoupling capacitors. Decoupling capacitors should be placed as close as possible
to the point of use and should avoid sharing vias with other decoupling capacitors.
Decoupling capacitor placement control should be done for the PHY as well as pass
transistors or regulators.
82574 GbE Controller—Design Considerations