WG82574L S LBA9 Intel, WG82574L S LBA9 Datasheet - Page 326

• Manufacturer Part Number: WG82574L S LBA9
• Description: CONTROLLER, ENET, INTEL 82574L, 64PQFN
• Manufacturer: Intel

Specifications of WG82574L S LBA9

• Ethernet Type: IEEE 802.3, IEEE 802.3u, IEEE 802.3ab
• Supply Voltage Range: 3V To 3.6V
• Operating Temperature Range: 0°C To +85°C
• Digital Ic Case Style: QFN
• No. Of Pins: 64
• Package / Case: QFN
• Interface Type: I2C, JTAG, PCI, SPI
• Rohs Compliant: Yes
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

10.2.4.7
10.2.4.8
10.2.4.9
326
Interrupt Auto Clear- EIAC (0x000DC; RW)
Interrupt Acknowledge Auto
Interrupt Vector Allocation Registers - IVAR (0x000E4; RW)
This register is only valid in MSI-X mode. It defines the allocation of the different
interrupt causes to one of the MSI-X vectors. Each INT_Alloc[i] (i=0…4) field is
indexing an entry in the MSI-X table structure and MSI-X PBA structure.
Reserved
EIAC_VALUE
Reserved
IAM_VALUE
INT_Alloc[0]
INT_Alloc_val[0] 3
INT_Alloc[1]
INT_Alloc_val[1] 7
INT_Alloc[2]
INT_Alloc_val[2] 11
INT_Alloc[3]
INT_Alloc_val[3] 15
Field
Field
Field
19:0
24:20
31:25
31:0
Bit(s)
Bit(s)
2:0
6:4
10:8
14:12
Bit(s)
0x0
0
0x0
0
0x0
0
0x0
0
0x0
0x0
0x0
0x0
Initial
Initial
Initial
Value
Value
Value
Defines the MSI-X vector assigned to the interrupt cause associated
with this entry. Valid values are 0 to 4 for MSI-X mode.
Note: Mapped to Receive Queue 0 (RxQ0). RxQ0 associates an
interrupt occurring in Rx queue 0 with a corresponding entry in the
MSI-X Allocation registers.
Enable bit for RxQ0.
Defines the MSI-X vector assigned to the interrupt cause associated
with this entry. Valid values are 0 to 4 for MSI-X mode.
Note: Mapped to Receive Queue 1 (RxQ1). RxQ1 associates an
interrupt occurring in Rx queue 0 with a corresponding entry in the
MSI-X Allocation registers.
Enable bit for RxQ1.
Defines the MSI-X vector assigned to the interrupt cause associated
with this entry. Valid values are 0 to 4 for MSI-X mode.
Note: Mapped to Transmit Queue 0 (TxQ0). TxQ0 associates an
interrupt occurring in Tx queue 0 with a corresponding entry in the
MSI-X Allocation registers.
Enable bit for TxQ0.
Defines the MSI-X vector assigned to the interrupt cause associated
with this entry. Valid values are 0 to 4 for MSI-X mode.
Note: Mapped to Transmit Queue 1 (TxQ1). TxQ1 associates an
interrupt occurring in Tx queue 1 with a corresponding entry in the
MSI-X Allocation registers.
Enable bit for TxQ1.
Reserved
Auto clear bits for the corresponding bits of ICR.
This register is relevant to MSI-X mode only, where read-to-clear can
not be used, as it might erase causes tied to other vectors. If any bits
are set in EIAC, the ICR register should not be read. Bits without auto
clear set, need to be cleared with write-to-clear.
Reserved
When the CTRL_EXT.IAME bit is set and the ICR.INT_ASSERT=1b, an
ICR read or write has the side effect of writing the contents of this
register to the IMC register.
–
Mask - IAM (0x000E0; RW)
82574 GbE Controller—Driver Programing Interface
Description
Description
Description