WG82574L S LBA9 Intel, WG82574L S LBA9 Datasheet - Page 414

• Manufacturer Part Number: WG82574L S LBA9
• Description: CONTROLLER, ENET, INTEL 82574L, 64PQFN
• Manufacturer: Intel

Specifications of WG82574L S LBA9

• Ethernet Type: IEEE 802.3, IEEE 802.3u, IEEE 802.3ab
• Supply Voltage Range: 3V To 3.6V
• Operating Temperature Range: 0°C To +85°C
• Digital Ic Case Style: QFN
• No. Of Pins: 64
• Package / Case: QFN
• Interface Type: I2C, JTAG, PCI, SPI
• Rohs Compliant: Yes
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

10.2.12.6
10.2.12.7
Note:
10.2.12.8
414
This register stores a copy of the Receive Data FIFO Tail register if the internal register
needs to be restored. This register is available for diagnostic purposes only, and should
not be written during normal operation.
Receive Data FIFO Packet Count - RDFPC (0x02430; RW)
This register reflects the number of receive packets that are currently in the receive
FIFO. This register is available for diagnostic purposes only, and should not be written
during normal operation.
Transmit Data FIFO Head Register - TDFH (0x03410; RW)
1. The initial value equals PBA.RXA times 128.
This register stores the head pointer of the on–chip transmit data FIFO. Since the
internal FIFO is organized in units of 64-bit words, this field contains the 64-bit offset of
the current Transmit FIFO Head. So a value of 0x8 in this register corresponds to an
offset of eight Qwords or 64 bytes into the transmit FIFO space. This register is
available for diagnostic purposes only, and should not be written during normal
operation.
This register’s address has been moved from where it was located in the previous
devices. However, for backwards compatibility, this register can also be accessed at its
alias offset of 0x08010. In addition, with the 82574, the value in this register contains
the offset of the transmit FIFO head relative to the beginning of the entire PBM space.
Alternatively, with the previous devices, the value in this register contains the relative
offset to the beginning of the transmit FIFO space (within the PBM space).
Transmit Data FIFO Tail Register - TDFT (0x03418; RW)
1. The initial value equals PBA.RXA times 128.
This register stores the head pointer of the on–chip transmit data FIFO. Since the
internal FIFO is organized in units of 64 bit words, this field contains the 64 bit offset of
the current Transmit FIFO Tail. So a value of “0x8” in this register corresponds to an
offset of 8 QWORDS or 64 bytes into the Transmit FIFO space. This register is available
for diagnostic purposes only, and should not be written during normal operation.
RX FIFO
Packet Count
Reserved
FIFO Tail
Reserved
FIFO Tail
Reserved
Field
Field
Field
12:0
31:13
12:0
31:13
12:0
31:13
Bit(s)
Bit(s)
Bit(s)
0x0
0x0
0x600
0x0
0x600
0x0
Initial
Initial
Initial
Value
Value
Value
1
1
The number of received packets currently in the RX FIFO.
Reads as 0x0. Should be written to 0x0 for future compatibility.
Transmit FIFO Head Pointer
Reads as 0x0. Should be written to 0x0 for future compatibility.
Transmit FIFO Tail Pointer
Reads as 0x0. Should be written to 0x0 for future compatibility.
82574 GbE Controller—Driver Programing Interface
Description
Description
Description