WG82574L S LBA9 Intel, WG82574L S LBA9 Datasheet - Page 192

• Manufacturer Part Number: WG82574L S LBA9
• Description: CONTROLLER, ENET, INTEL 82574L, 64PQFN
• Manufacturer: Intel

Specifications of WG82574L S LBA9

• Ethernet Type: IEEE 802.3, IEEE 802.3u, IEEE 802.3ab
• Supply Voltage Range: 3V To 3.6V
• Operating Temperature Range: 0°C To +85°C
• Digital Ic Case Style: QFN
• No. Of Pins: 64
• Package / Case: QFN
• Interface Type: I2C, JTAG, PCI, SPI
• Rohs Compliant: Yes
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

Table 45.
7.7.2.1
7.7.3
192
Chronological Order of Events for Sync and Path Delay
TimeSync Indications in Rx and Tx Packet Descriptors
Some indications need to be transferred between software and hardware regarding PTP
packets. On the Tx path the software should set the TST bit in the ExtCMD field in the
Tx advanced descriptor.
On the Rx path, hardware has two indications to transfer to software, one is to indicate
that this packet is a PTP packet (no matter if timestamp taken or not) this is also for
other types of PTP packets needed for management of the protocol this bit is set only
for the L2 type of packets (the PTP packet is identified according to its Ethertype). PTP
packets have the PACKETTYPE field set to 0xE to indicate that the Etype matches the
filter number set by software to filter PTP packets. The UDP type of PTP packets don’t
need such indication since the port number (319 for event and 320 all the rest PTP
packets) directs the packets toward the time sync application. The second indication is
the TST bit in the Extended Status field of the Rx descriptor this bit indicates to the
software that time stamp was taken for this packet. Software needs to access the time
stamp registers to get the timestamp values.
Hardware Time Sync Elements
All time sync hardware elements are reset to their initial values as defined in the
registers section upon MAC reset.
Generate a sync packet with timestamp notification in descriptor.
Timestamp the packet and store the value in registers (T1).
Timestamp incoming sync packet, store the value in register and store the
sourceID and sequenceID in registers (T2).
Read the timestamp from register put in a Follow_Up packet and send.
Once got the Follow_Up store T2 from registers and T1 from Follow_Up
packet.
Generate a Delay_Req packet with timestamp notification in descriptor
Timestamp the packet and store the value in registers (T3).
Timestamp incoming Delay_Req packet, store the value in register and
store the sourceID and sequenceID in registers (T4).
Read the timestamp from register and send back to Slave using a
Delay_Response packet.
Once got the Delay_Response packet calculate offset using T1, T2, T3 and
T4 values.
Action
82574 GbE Controller—Inline Functions
HW
SW
SW
HW
SW
SW
SW
HW
SW
HW
Responsibility
Node Role
Master
Master
Slave
Master
Slave
Slave
Slave
Master
Master
Slave